lab5.map.qmsg

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{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "instruction prog_ram.v(6) " "Warning: Verilog HDL Always Construct warning at prog_ram.v(6): variable \"instruction\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"instruction\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 6 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cpu:cpu\|mem_read_addr\[3\] data_in GND " "Warning: Reduced register \"cpu:cpu\|mem_read_addr\[3\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 4 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cpu:cpu\|mem_write_addr\[3\] data_in GND " "Warning: Reduced register \"cpu:cpu\|mem_write_addr\[3\]\" with stuck data_in port to stuck value GND" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 4 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|lab2_sim\|cpu:cpu\|flag 3 0 " "Info: State machine \"\|lab2_sim\|cpu:cpu\|flag\" contains 3 states and 0 state bits" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|lab2_sim\|cpu:cpu\|flag " "Info: Selected Auto state machine encoding method for state machine \"\|lab2_sim\|cpu:cpu\|flag\"" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|lab2_sim\|cpu:cpu\|flag " "Info: Encoding result for state machine \"\|lab2_sim\|cpu:cpu\|flag\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cpu:cpu\|flag.00 " "Info: Encoded state bit \"cpu:cpu\|flag.00\"" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cpu:cpu\|flag.10 " "Info: Encoded state bit \"cpu:cpu\|flag.10\"" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cpu:cpu\|flag.01 " "Info: Encoded state bit \"cpu:cpu\|flag.01\"" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lab2_sim\|cpu:cpu\|flag.00 000 " "Info: State \"\|lab2_sim\|cpu:cpu\|flag.00\" uses code string \"000\"" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lab2_sim\|cpu:cpu\|flag.01 101 " "Info: State \"\|lab2_sim\|cpu:cpu\|flag.01\" uses code string \"101\"" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lab2_sim\|cpu:cpu\|flag.10 110 " "Info: State \"\|lab2_sim\|cpu:cpu\|flag.10\" uses code string \"110\"" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0}  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 12 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus50sp1/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/lpm_mult.tdf" 274 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus50sp1/libraries/megafunctions/multcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/multcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 multcore " "Info: Found entity 1: multcore" {  } { { "multcore.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/multcore.tdf" 175 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus50sp1/libraries/megafunctions/mpar_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/mpar_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mpar_add " "Info: Found entity 1: mpar_add" {  } { { "mpar_add.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/mpar_add.tdf" 60 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus50sp1/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus50sp1/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus50sp1/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[0\] " "Warning: Latch prog_ram:prog_ram\|instruction\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[1\] " "Warning: Latch prog_ram:prog_ram\|instruction\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[2\] " "Warning: Latch prog_ram:prog_ram\|instruction\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[4\] " "Warning: Latch prog_ram:prog_ram\|instruction\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[5\] " "Warning: Latch prog_ram:prog_ram\|instruction\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[8\] " "Warning: Latch prog_ram:prog_ram\|instruction\[8\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[9\] " "Warning: Latch prog_ram:prog_ram\|instruction\[9\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[10\] " "Warning: Latch prog_ram:prog_ram\|instruction\[10\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "prog_ram:prog_ram\|instruction\[11\] " "Warning: Latch prog_ram:prog_ram\|instruction\[11\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA cpu:cpu\|ram_addr\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu\|ram_addr\[4\]" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0}  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "instruction\[3\] GND " "Warning: Pin \"instruction\[3\]\" stuck at GND" {  } { { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 4 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "instruction\[6\] GND " "Warning: Pin \"instruction\[6\]\" stuck at GND" {  } { { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 4 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "instruction\[7\] GND " "Warning: Pin \"instruction\[7\]\" stuck at GND" {  } { { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 7 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "241 " "Info: Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "28 " "Info: Implemented 28 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "211 " "Info: Implemented 211 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 41 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 01:18:55 2007 " "Info: Processing ended: Wed Oct 10 01:18:55 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}