lab5.map.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 10 01:18:47 2007 " "Info: Processing started: Wed Oct 10 01:18:47 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lab5 -c lab5 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab5 -c lab5" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Info: Found entity 1: cpu" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lab2_sim.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lab2_sim.v" { { "Info" "ISGN_ENTITY_NAME" "1 lab2_sim " "Info: Found entity 1: lab2_sim" {  } { { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "memory.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 memory " "Info: Found entity 1: memory" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "prog_ram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file prog_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 prog_ram " "Info: Found entity 1: prog_ram" {  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lab2_sim " "Info: Elaborating entity \"lab2_sim\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Info: Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" {  } { { "lab2_sim.v" "cpu" { Text "C:/altera/lab5/lab2_sim.v" 9 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(26) " "Warning: Verilog HDL assignment warning at cpu.v(26): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(32) " "Warning: Verilog HDL assignment warning at cpu.v(32): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(35) " "Warning: Verilog HDL assignment warning at cpu.v(35): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(39) " "Warning: Verilog HDL assignment warning at cpu.v(39): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 39 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(43) " "Warning: Verilog HDL assignment warning at cpu.v(43): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(47) " "Warning: Verilog HDL assignment warning at cpu.v(47): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(51) " "Warning: Verilog HDL assignment warning at cpu.v(51): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(55) " "Warning: Verilog HDL assignment warning at cpu.v(55): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 55 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(59) " "Warning: Verilog HDL assignment warning at cpu.v(59): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(74) " "Warning: Verilog HDL assignment warning at cpu.v(74): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(90) " "Warning: Verilog HDL assignment warning at cpu.v(90): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 90 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.v(98) " "Warning: Verilog HDL assignment warning at cpu.v(98): truncated value with size 32 to match size of target (5)" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 98 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "cpu.v(31) " "Warning: (10270) Verilog HDL statement warning at cpu.v(31): incomplete Case Statement has no default case item" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 31 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:memory " "Info: Elaborating entity \"memory\" for hierarchy \"memory:memory\"" {  } { { "lab2_sim.v" "memory" { Text "C:/altera/lab5/lab2_sim.v" 10 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "memory.v(19) " "Warning: (10270) Verilog HDL statement warning at memory.v(19): incomplete Case Statement has no default case item" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "memory.v(27) " "Warning: (10270) Verilog HDL statement warning at memory.v(27): incomplete Case Statement has no default case item" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 27 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "prog_ram prog_ram:prog_ram " "Info: Elaborating entity \"prog_ram\" for hierarchy \"prog_ram:prog_ram\"" {  } { { "lab2_sim.v" "prog_ram" { Text "C:/altera/lab5/lab2_sim.v" 11 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "prog_ram.v(7) " "Warning: (10270) Verilog HDL statement warning at prog_ram.v(7): incomplete Case Statement has no default case item" {  } { { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 7 0 0 } }  } 0}