lab5.hif

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sin4
cin0
cin1
cin2
cin3
cin4
sout0
sout1
sout2
sout3
sout4
cout0
cout1
cout2
cout3
cout4
}
# end
# entity
altshift
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|altshift.tdf
1118942318
6
# storage
db|lab5.(11).cnf
db|lab5.(11).cnf
# user_parameter {
WIDTH
5
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
result0
result1
result2
result3
result4
}
# end
# entity
altshift
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|altshift.tdf
1118942318
6
# storage
db|lab5.(12).cnf
db|lab5.(12).cnf
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
result0
}
# end
# entity
mpar_add
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|mpar_add.tdf
1118942318
6
# storage
db|lab5.(13).cnf
db|lab5.(13).cnf
# user_parameter {
size
6
PARAMETER_UNKNOWN
USR
width
2
PARAMETER_UNKNOWN
USR
REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LEVEL
2
PARAMETER_UNKNOWN
USR
TOT_LEVELS
3
PARAMETER_UNKNOWN
USR
STAGE
2
PARAMETER_UNKNOWN
USR
TOT_STAGES
3
PARAMETER_UNKNOWN
USR
INT_LATENCY
1
PARAMETER_UNKNOWN
USR
PREV_SING_SIZE
6
PARAMETER_UNKNOWN
USR
BOOTH_ADDER
NO
PARAMETER_UNKNOWN
USR
CREATE_MS_BOOTH_ADDER
NO
PARAMETER_UNKNOWN
USR
MPARADD_OP_MODE
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0_0
data0_1
data0_2
data0_3
data0_4
data0_5
data1_0
data1_1
data1_2
data1_3
data1_4
data1_5
result0
result1
result2
result3
result4
result5
result6
result7
}
# include_file {
..|quartus50sp1|libraries|megafunctions|lpm_add_sub.inc
1107574408
..|quartus50sp1|libraries|megafunctions|mpar_add.inc
1107575144
}
# end
# entity
lpm_add_sub
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|lpm_add_sub.tdf
1118942312
6
# storage
db|lab5.(14).cnf
db|lab5.(14).cnf
# user_parameter {
LPM_WIDTH
6
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
DEFAULT
PARAMETER_UNKNOWN
DEF
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
6
PARAMETER_UNKNOWN
USR
REGISTERED_AT_END
1
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_d0h
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
datab0
datab1
datab2
datab3
datab4
datab5
result0
result1
result2
result3
result4
result5
}
# include_file {
..|quartus50sp1|libraries|megafunctions|aglobal50.inc
1118942284
..|quartus50sp1|libraries|megafunctions|bypassff.inc
1107573920
..|quartus50sp1|libraries|megafunctions|altshift.inc
1107573438
..|quartus50sp1|libraries|megafunctions|alt_stratix_add_sub.inc
1107572606
..|quartus50sp1|libraries|megafunctions|addcore.inc
1107572218
..|quartus50sp1|libraries|megafunctions|look_add.inc
1107574364
..|quartus50sp1|libraries|megafunctions|alt_mercury_add_sub.inc
1107572592
}
# end
# entity
addcore
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|addcore.tdf
1118942312
6
# storage
db|lab5.(15).cnf
db|lab5.(15).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
6
PARAMETER_UNKNOWN
USR
REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
DIRECTION
DEFAULT
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
datab0
datab1
datab2
datab3
datab4
datab5
result0
result1
result2
result3
result4
result5
}
# include_file {
..|quartus50sp1|libraries|megafunctions|aglobal50.inc
1118942284
..|quartus50sp1|libraries|megafunctions|addcore.inc
1107572218
..|quartus50sp1|libraries|megafunctions|a_csnbuffer.inc
1107571892
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|a_csnbuffer.tdf
1118942312
6
# storage
db|lab5.(16).cnf
db|lab5.(16).cnf
# user_parameter {
WIDTH
6
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sout0
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|a_csnbuffer.tdf
1118942312
6
# storage
db|lab5.(17).cnf
db|lab5.(17).cnf
# user_parameter {
WIDTH
6
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sin1
sin2
sin3
sin4
sin5
cin0
cin1
cin2
cin3
cin4
cin5
sout0
sout1
sout2
sout3
sout4
sout5
cout0
cout1
cout2
cout3
cout4
cout5
}
# end
# entity
altshift
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|altshift.tdf
1118942318
6
# storage
db|lab5.(18).cnf
db|lab5.(18).cnf
# user_parameter {
WIDTH
6
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
result0
result1
result2
result3
result4
result5
}
# end
# entity
altshift
# case_insensitive
# source_file
..|quartus50sp1|libraries|megafunctions|altshift.tdf
1118942318
6
# storage
db|lab5.(19).cnf
db|lab5.(19).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
result0
result1
result2
result3
result4
result5
result6
result7
}
# end
# entity
lab2_sim
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lab2_sim.v
1191945046
7
# storage
db|lab5.(0).cnf
db|lab5.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
prog_ram
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
prog_ram.v
1191948697
7
# storage
db|lab5.(3).cnf
db|lab5.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
prog_ram:prog_ram
}
# end
# entity
memory
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
memory.v
1191949883
7
# storage
db|lab5.(2).cnf
db|lab5.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
memory:memory
}
# end
# entity
cpu
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
1191950320
7
# storage
db|lab5.(1).cnf
db|lab5.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cpu:cpu
}
# end
# complete