memory.v

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module memory(data_in,data_out,mem_write_addr,mem_read_addr,clock,rst); 
   input [3:0] data_in;
   output [3:0] data_out;
   input [3:0] mem_write_addr;
   input [3:0] mem_read_addr;
   input clock,rst;
   reg [3:0] data_out,a,b,c,d,e,f;
   
  
    always@(posedge clock or negedge rst)
begin
if(rst==0)
 begin
       a=4'd0;
       b=4'd4;
   end
else 
      begin
      case(mem_read_addr)
          4'b0000:data_out=a;
          4'b0001:data_out=b;
          4'b0010:data_out=c;
          4'b0011:data_out=d;
          4'b0100:data_out=e;
          4'b0101:data_out=f;
      endcase
      case(mem_write_addr)
          4'b0000:a=data_in;
          4'b0001:b=data_in;
          4'b0010:c=data_in;
          4'b0011:d=data_in;
          4'b0100:e=data_in;
          4'b0101:f=data_in;
      endcase
      
      end
end      
endmodule