ml674001.h

T-Kernel下PCF8563的驱动程序开发

/* bit field of DBWC register */
#define DBWC_DBDRAM0    (0x00000000)    /* DRAM disable */
#define DBWC_DBDRAM8    (0x00000001)    /* 8bit width */
#define DBWC_DBDRAM16   (0x00000002)    /* 16bit width */

/* bit field of DRMC register */
#define DRMC_8bit       (0x00000000)    /* DRAM column length : 8bit */
#define DRMC_9bit       (0x00000001)    /* DRAM column length : 9bit */
#define DRMC_10bit      (0x00000002)    /* DRAM column length : 10bit */
#define DRMC_SDRAM      (0x00000000)    /* DRAM architecture : SDRAM */
#define DRMC_EDO        (0x00000004)    /* DRAM architecture : EDO-DRAM */
#define DRMC_2CLK       (0x00000000)    /* SDRAM pre-charge latency : 2clock */
#define DRMC_CAS        (0x00000010)    /* SDRAM pre-charge latency : same as CAS latency */
#define DRMC_PD_DIS     (0x00000000)    /* automatic shift to SDRAM power down mode : disable */
#define DRMC_PD_EN      (0x00000040)    /* automatic shift to SDRAM power down mode : enable */
#define DRMC_CBR_STOP   (0x00000000)    /* CBR refresh : stop */
#define DRMC_CBR_EXE    (0x00000080)    /* CBR refresh : execution */

/* bit field of DRPC register */
#define DRPC_DRAMSPEC   (0x0000000F)    /* DRAMSPEC[3:0] */

/* bit field of SDMD register */
#define SDMD_CL2    (0x00000000)    /* SDRAM CAS latency : 2 */
#define SDMD_CL3    (0x00000001)    /* SDRAM CAS latency : 3 */
#define SDMD_MODEWR (0x00000080)    /* setting operation : valid */

/* bit field of DCMD register */
#define DCMD_S_NOP      (0x00000000)    /* No operation */
#define DCMD_S_PALL     (0x00000004)    /* SDRAM all bank pre-charge command */
#define DCMD_S_REF      (0x00000005)    /* SDRAM CBR refresh command */
#define DCMD_S_SELF     (0x00000006)    /* SDRAM self refresh start command */
#define DCMD_S_SREX     (0x00000007)    /* SDRAM self refresh stop command */
#define DCMD_EDO_NOP    (0x00000000)    /* No operation */
#define DCMD_EDO_PC     (0x00000004)    /* EDO-DRAM pre-charge cycle */
#define DCMD_EDO_REF    (0x00000005)    /* EDO-DRAM CBR refresh cycle */
#define DCMD_EDO_SELF   (0x00000006)    /* EDO-DRAM self refresh start cycle */
#define DCMD_EDO_SREX   (0x00000007)    /* EDO-DRAM self refresh stop cycle */

/* bit field of RFSH0 register */
#define RFSH0_RCCON  (0x00000001)   /* RCCON bit, refresh frequency = refclk(RFSH1)*2(RCCON=0) */
#define RFSH0_SINGLE (0x00000000)   /* RCCON bit, refresh frequency = refclk(RFSH1)  (RCCON=1) */
/* bit field of RFSH1 register */
#define RFSH1_RFSEL1    (0x000007FF)    /* RFSEL1[10:0], refckl(RFSH1) = CCLK/RFSEL1[10:0] */

/* bit field of PDWC register */
#define PDWC_1  (0x00000000)    /* when  1 or more cycles of idol state continue,
                                   it shifts to power down mode. */
#define PDWC_2  (0x00000001)    /*                   :                   */
#define PDWC_3  (0x00000002)    /*                   :                   */
#define PDWC_4  (0x00000003)    /*                   :                   */
#define PDWC_5  (0x00000004)    /*                   :                   */
#define PDWC_6  (0x00000005)    /*                   :                   */
#define PDWC_7  (0x00000006)    /*                   :                   */
#define PDWC_8  (0x00000007)    /*                   :                   */
#define PDWC_9  (0x00000008)    /*                   :                   */
#define PDWC_10 (0x00000009)    /*                   :                   */
#define PDWC_11 (0x0000000A)    /*                   :                   */
#define PDWC_12 (0x0000000B)    /*                   :                   */
#define PDWC_13 (0x0000000C)    /*                   :                   */
#define PDWC_14 (0x0000000D)    /*                   :                   */
#define PDWC_15 (0x0000000E)    /*                   :                   */
#define PDWC_16 (0x0000000F)    /* when 16 or more cycles of idol state continue,
                                   it shifts to power down mode. */



/*****************************************************/
/*    SSIO control register                          */
/*****************************************************/
#define SSIO_BASE   (0xB7B01000)        /* base address */
#define SSIOBUF     (SSIO_BASE+0x00)    /* transmiting/receiving buffer register (RW,8,0x00) */
#define SSIOST      (SSIO_BASE+0x04)    /* SSIO status register (RW,8,0x00) */
#define SSIOINT     (SSIO_BASE+0x08)    /* SSIO interrupt demand register (RW,8,0x00) */
#define SSIOINTEN   (SSIO_BASE+0x0C)    /* SSIO interrupt enable register (RW,8,0x00) */
#define SSIOCON     (SSIO_BASE+0x10)    /* SSIO control register (RW,8,0x00) */
#define SSIOTSCON   (SSIO_BASE+0x14)    /* SSIO test control register (RW,8,0x00) */

/* bit field of SSIOBUF register */
#define SSIOSTA_DUMMY   (0xFF)

/* bit field of SSIOST register */
#define SSIOSTA_BUSY    (0x01)  /* transmiting/receiving buffer busy */
#define SSIOSTA_OERR    (0x02)  /* overrun error */

/* bit field of SSIOINT register */
#define SSIOCON_TXCMP   (0x01)  /* transmit complete */
#define SSIOCON_RXCMP   (0x02)  /* receive complete */
#define SSIOCON_TREMP   (0x04)  /* transmit empty */

/* bit field of SSIOINTEN register */
#define SSIOCON_TXCMPEN (0x01)  /* transmit complete enable */
#define SSIOCON_RXCMPEN (0x02)  /* receive complete enable */
#define SSIOCON_TREMPEN (0x04)  /* transmit empty enable */

/* bit field of SSIOCON register */
#define SSIOCON_SLLSB   (0x00)  /* LSB */
#define SSIOCON_SLMSB   (0x20)  /* MSB */
#define SSIOCON_SLAVE   (0x10)  /* Slave */
#define SSIOCON_MASTER  (0x00)  /* Master */
#define SSIOCON_8CCLK   (0x00)  /* 1/8CCLK */
#define SSIOCON_16CCLK  (0x01)  /* 1/16CCLK */
#define SSIOCON_32CCLK  (0x02)  /* 1/32CCLK */

/* bit field of SSIOTSCON register */
#define SSIOTSCON_LBTST (0x80)  /* loop back test mode on*/
#define SSIOTSCON_NOTST (0x00)  /* test mode off */

/*****************************************************/
/*    I2C control register                          */
/*****************************************************/
#define I2C_BASE    (0xB7800000)    /* base address */
#define I2CCON      (I2C_BASE+0x00) /* I2C control register (RW,8,0x00) */
#define I2CSAD      (I2C_BASE+0x04) /* I2C slave address mode setting register (RW,8,0x00) */
#define I2CCLR      (I2C_BASE+0x08) /* I2C transmit speed setting register (RW,8,0x00) */
#define I2CSR       (I2C_BASE+0x0C) /* I2C status register (R,8,0x00) */
#define I2CIR       (I2C_BASE+0x10) /* I2C interrupt demand register (RW,8,0x00) */
#define I2CIMR      (I2C_BASE+0x14) /* I2C interrupt mask register  (RW,8,0x00) */
#define I2CDR       (I2C_BASE+0x18) /* I2C transmiting/receiving buffer register (RW,8,0x00) */
#define I2CBC       (I2C_BASE+0x1C) /* I2C transmit speed setting register (RW,8,0x00) */

/* bit field of I2CCON register */
#define I2CCON_EN       (0x01)  /* restart sequence start */
#define I2CCON_OC       (0x02)  /* I2C-bus hold */
#define I2CCON_STCM     (0x04)  /* communication start */
#define I2CCON_RESTR    (0x08)  /* carry out restart */
#define I2CCON_START    (0x10)  /* exist START byte */

/* bit field of I2CSAD register */
#define I2CSAD_RW_SND   (0x00)  /* data transmiting mode */
#define I2CSAD_RW_REC   (0x01)  /* data receiving mode */

/* bit field of I2CCLR register */
#define I2CCLR_CMD1 (0x00)  /* Standard-mode */
#define I2CCLR_CMD4 (0x01)  /* Fast-mode */

/* bit field of I2CSR register */
#define I2CSR_DAK   (0x01)  /* data ACKnowledge no receive */
#define I2CSR_AAK   (0x02)  /* slave address ACKnowledge no receive */

/* bit field of I2CIR register */
#define I2CIR_IR    (0x01)  /* interrupt demand */

/* bit field of I2CIMR register */
#define I2CIMR_MF   (0x01)  /* interrupt mask set */

/* bit field of I2CDR register */

/* bit field of I2CBC register */
#define I2CBC_100K33    (0x2A)  /* HCLK=33MHz,I2CMD=100kHz */
#define I2CBC_400K33    (0x0B)  /* HCLK=33MHz,I2CMD=400kHz */
#define I2CBC_100K25    (0x20)  /* HCLK=25MHz,I2CMD=100kHz */
#define I2CBC_400K25    (0x08)  /* HCLK=25MHz,I2CMD=400kHz */
#define I2CBC_100K20    (0x19)  /* HCLK=20MHz,I2CMD=100kHz */
#define I2CBC_400K20    (0x07)  /* HCLK=20MHz,I2CMD=400kHz */


/*****************************************************/
/*    Chip configuration register                    */
/*****************************************************/
#define CCR_BASE    (0xB7000000)    /* base address */
#define GPCTL       (CCR_BASE+0x00) /* port function control register (RW,16,0x0000) */
#define BCKCTL      (CCR_BASE+0x04) /* clock control register (RW,16,0x0000) */
#define CSSW        (CCR_BASE+0x08) /* external ROM/RAM chip cell control register (RW,16,0x0000) */
#define ROMSEL      (CCR_BASE+0x0C) /* ROM select register (RW,8,0x00) */

/* bit field of GPCTL */
#define GPCTL_GPCTL     (0x7FFF)    /* GPCTL[14:0] */
#define GPCTL_UART      (0x0001)    /* select 2nd function (UART) */
#define GPCTL_SIO       (0x0002)    /* select 2nd function (SIO) */
#define GPCTL_EXBUS     (0x0004)    /* select 2nd function (external bus) */
#define GPCTL_DMA0      (0x0008)    /* select 2nd function (DMA CH0) */
#define GPCTL_DMA1      (0x0010)    /* select 2nd function (DMA CH1) */
#define GPCTL_PWM       (0x0020)    /* select 2nd function (PWM) */
#define GPCTL_XWAIT     (0x0040)    /* select 2nd function (external bus wait input) */
#define GPCTL_XWR       (0x0080)    /* select 2nd function (external bus data direction) */
#define GPCTL_SSIO0     (0x0100)    /* select 2nd function (SSIO) */
#define GPCTL_I2C       (0x0200)    /* select 2nd function (I2C) */
#define GPCTL_EXINT0    (0x0400)    /* select 2nd function (EXINT0) */
#define GPCTL_EXINT1    (0x0800)    /* select 2nd function (EXINT1) */
#define GPCTL_EXINT2    (0x1000)    /* select 2nd function (EXINT2) */
#define GPCTL_EXINT3    (0x2000)    /* select 2nd function (EXINT3) */
#define GPCTL_EFIQ_N    (0x4000)    /* select 2nd function (EFIQ_N) */

/* bit field of BCKCTL */
#define BCKCTL_AD   (0x0001)    /* ADC */
#define BCKCTL_PWM  (0x0002)    /* PWM */
#define BCKCTL_ART0 (0x0004)    /* auto reload timer(CH0) */
#define BCKCTL_ART1 (0x0008)    /* auto reload timer(CH1) */
#define BCKCTL_ART2 (0x0010)    /* auto reload timer(CH2) */
#define BCKCTL_ART3 (0x0020)    /* auto reload timer(CH3) */
#define BCKCTL_ART4 (0x0040)    /* auto reload timer(CH4) */
#define BCKCTL_ART5 (0x0080)    /* auto reload timer(CH5) */
#define BCKCTL_DRAM (0x0100)    /* DRAM controller */
#define BCKCTL_DMA  (0x0200)    /* DMAC */
#define BCKCTL_UART (0x0400)    /* UART */
#define BCKCTL_SSIO (0x0800)    /* SSIO */
#define BCKCTL_I2C  (0x1000)    /* I2C */

/* bit field of CSSW register */
#define CSSW_CHG        (0x0001)    /* CHG bit */
#define CSSW_CHG_SET    (0xA5A5)    /* set CHG */
#define CSSW_CHG_RESET  (0x5A5A)    /* reset CHG */


/*****************************************************/
/*    interrupt number                               */
/*****************************************************/
#define INT_SYSTEM_TIMER    0
#define INT_WDT             1
#define INT_IVT             2
#define INT_GPIOA           4
#define INT_GPIOB           5
#define INT_GPIOC           6
#define INT_GPIOD           7
#define INT_GPIOE           7
#define INT_SOFTIRQ         8
#define INT_UART            9
#define INT_SIO             10
#define INT_AD              11
#define INT_PWM0            12
#define INT_PWM1            13
#define INT_SSIO            14
#define INT_I2C             15
#define INT_TIMER0          16
#define INT_TIMER1          17
#define INT_TIMER2          18
#define INT_TIMER3          19
#define INT_TIMER4          20
#define INT_TIMER5          21
#define INT_EX0             22
#define INT_DMA0            24
#define INT_DMA1            25
#define INT_EX1             26
#define INT_EX2             28
#define INT_EX3             31

#ifdef __cplusplus
};      /* End of 'extern "C"' */
#endif
#endif  /* End of ML674001.h */