ml674001.h

T-Kernel下PCF8563的驱动程序开发

#define GPIPD       (PCR_BASE+0x70) /* port D interrupt Polarity (RW,16,0x0000) */
#define GPISD       (PCR_BASE+0x74) /* port D interrupt Status (RW,16,0x0000) */

#define GPPOE       (PCR_BASE+0x80) /* port E Output register (RW,16,--) */
#define GPPIE       (PCR_BASE+0x84) /* port E Input register (RW,16,--) */
#define GPPME       (PCR_BASE+0x88) /* port E Mode register (RW,16,0x0000) */
#define GPIEE       (PCR_BASE+0x8C) /* port E interrupt enable (RW,16,0x0000) */
#define GPIPE       (PCR_BASE+0x90) /* port E interrupt Polarity (RW,16,0x0000) */
#define GPISE       (PCR_BASE+0x94) /* port E interrupt Status (RW,16,0x0000) */

/* bit field of GPPOA/GPPOB/GPPOC/GPPOD/GPPOE register */
#define GPPOA_GPPOA (0x00FF)    /* GPPOA[7:0] */
#define GPPOB_GPPOB (0x00FF)    /* GPPOB[7:0] */
#define GPPOC_GPPOC (0x00FF)    /* GPPOC[7:0] */
#define GPPOD_GPPOD (0x00FF)    /* GPPOD[7:0] */
#define GPPOE_GPPOE (0x03FF)    /* GPPOE[9:0] */

/* bit field of GPPIA/GPPIB/GPPIC/GPPID/GPPIE register */
#define GPPIA_GPPIA (0x00FF)    /* GPPIA[7:0] */
#define GPPIB_GPPIB (0x00FF)    /* GPPIB[7:0] */
#define GPPIC_GPPIC (0x00FF)    /* GPPIC[7:0] */
#define GPPID_GPPID (0x00FF)    /* GPPID[7:0] */
#define GPPIE_GPPIE (0x03FF)    /* GPPIE[9:0] */

/* bit field of GPPMA/GPPMB/GPPMC/GPPMD/GPPME register */
#define GPPMA_GPPMA (0x00FF)    /* GPPMA[7:0] 0:input, 1:output */
#define GPPMB_GPPMB (0x00FF)    /* GPPMB[7:0] 0:input, 1:output */
#define GPPMC_GPPMC (0x00FF)    /* GPPMC[7:0] 0:input, 1:output */
#define GPPMD_GPPMD (0x00FF)    /* GPPMD[7:0] 0:input, 1:output */
#define GPPME_GPPME (0x03FF)    /* GPPME[9:0] 0:input, 1:output */

/* bit field of GPIEA/GPIEB/GPIEC/GPIED/GPIEE register */
#define GPIEA_GPIEA (0x00FF)    /* GPIEA[7:0] 0:interrupt disable, 1:interrupt enable */
#define GPIEB_GPIEB (0x00FF)    /* GPIEB[7:0] 0:interrupt disable, 1:interrupt enable */
#define GPIEC_GPIEC (0x00FF)    /* GPIEC[7:0] 0:interrupt disable, 1:interrupt enable */
#define GPIED_GPIED (0x00FF)    /* GPIED[7:0] 0:interrupt disable, 1:interrupt enable */
#define GPIEE_GPIEE (0x03FF)    /* GPIEE[9:0] 0:interrupt disable, 1:interrupt enable */

/* bit field of GPIPA/GPIPB/GPIPC/GPIPD/GPIPE register */
#define GPIPA_GPIPA (0x00FF)    /* GPIPA[7:0] 0:falling edge, 1:rising edge */
#define GPIPB_GPIPB (0x00FF)    /* GPIPB[7:0] 0:falling edge, 1:rising edge */
#define GPIPC_GPIPC (0x00FF)    /* GPIPC[7:0] 0:falling edge, 1:rising edge */
#define GPIPD_GPIPD (0x00FF)    /* GPIPD[7:0] 0:falling edge, 1:rising edge */
#define GPIPE_GPIPE (0x03FF)    /* GPIPE[9:0] 0:falling edge, 1:rising edge */

/* bit field of GPISA/GPISB/GPISC/GPISD/GPISE register */
#define GPISA_GPISA (0x00FF)    /* GPISA[7:0] 0:interrupt not occurred, 1:interrupt occurred */
#define GPISB_GPISB (0x00FF)    /* GPISB[7:0] 0:interrupt not occurred, 1:interrupt occurred */
#define GPISC_GPISC (0x00FF)    /* GPISC[7:0] 0:interrupt not occurred, 1:interrupt occurred */
#define GPISD_GPISD (0x00FF)    /* GPISD[7:0] 0:interrupt not occurred, 1:interrupt occurred */
#define GPISE_GPISE (0x03FF)    /* GPISE[9:0] 0:interrupt not occurred, 1:interrupt occurred */


/*****************************************************/
/*    ADC control register                           */
/*****************************************************/
#define ADC_BASE    (0xB6001000)    /* base address */
#define ADCON0      (ADC_BASE+0x00) /* ADC control 0 register (RW,16,0x0000) */
#define ADCON1      (ADC_BASE+0x04) /* ADC control 1 register (RW,16,0x0000) */
#define ADCON2      (ADC_BASE+0x08) /* ADC control 2 register (RW,16,0x0003) */
#define ADINT       (ADC_BASE+0x0C) /* AD interrupt control register (RW,16,0x0000) */
#define ADFINT      (ADC_BASE+0x10) /* AD Forced interrupt register (RW,16,0x0000) */
#define ADR0        (ADC_BASE+0x14) /* AD Result 0 register (RW,16,0x0000) */
#define ADR1        (ADC_BASE+0x18) /* AD Result 1 register (RW,16,0x0000) */
#define ADR2        (ADC_BASE+0x1C) /* AD Result 2 register (RW,16,0x0000) */
#define ADR3        (ADC_BASE+0x20) /* AD Result 3 register (RW,16,0x0000) */


/* bit field of ADCON0 register */
#define ADCON0_ADSNM    (0x0003)    /* ADSNM[1:0] */
#define ADCON0_CH0_3    (0x0000)    /* CH0->CH1->CH2->CH3 */
#define ADCON0_CH1_3    (0x0001)    /* CH1->CH2->CH3 */
#define ADCON0_CH2_3    (0x0002)    /* CH2->CH3 */
#define ADCON0_CH3_3    (0x0003)    /* CH3 */
#define ADCON0_ADRUN    (0x0010)    /* AD conversion start */
#define ADCON0_SCNC     (0x0040)    /* Stop after a round */

/* bit field of ADCON1 register */
#define ADCON1_ADSTM    (0x0003)    /* ADSTM[1:0] */
#define ADCON1_CH0      (0x0000)    /* CH0 */
#define ADCON1_CH1      (0x0001)    /* CH1 */
#define ADCON1_CH2      (0x0002)    /* CH2 */
#define ADCON1_CH3      (0x0003)    /* CH3 */
#define ADCON1_STS      (0x0010)    /* AD conversion start */

/* bit field of ADCON2 register */
#define ADCON2_ACKSEL   (0x0003)    /* ACKSEL[1:0] */
#define ADCON2_CLK2     (0x0001)    /* CPUCLK/2 */
#define ADCON2_CLK4     (0x0002)    /* CPUCLK/4 */
#define ADCON2_CLK8     (0x0003)    /* CPUCLK/8 */

/* bit field of ADINT register */
#define ADINT_INTSN     (0x0001)    /* AD conversion of ch7 finished (scan mode) */
#define ADINT_INTST     (0x0002)    /* AD conversion finished (select mode) */
#define ADINT_ADSNIE    (0x0004)    /* enable interrupt (scan mode) */
#define ADINT_ADSTIE    (0x0008)    /* enable interrupt (select mode) */

/* bit field of ADFINT register */
#define ADFINT_ADFAS    (0x0001)    /* Assert interrupt signal */

/* bit field of ADR0,ADR1,ADR2,ADR3 register */
#define ADR0_DT0    (0x03FF)    /* DT0[9:0] AD result */
#define ADR1_DT1    (0x03FF)    /* DT1[9:0] AD result */
#define ADR2_DT2    (0x03FF)    /* DT2[9:0] AD result */
#define ADR3_DT3    (0x03FF)    /* DT3[9:0] AD result */


/*****************************************************/
/*    DMA control register                           */
/*****************************************************/
#define DMA_BASE    (0x7BE00000)        /* base address */
#define DMAMOD      (DMA_BASE+0x0000)   /* DMA Mode register (RW,32,0x00000000) */
#define DMASTA      (DMA_BASE+0x0004)   /* DMA Status register (R,32,0x00000000) */
#define DMAINT      (DMA_BASE+0x0008)   /* DMA interrupt Status register (R,32,0x00000000) */
#define DMACMSK0    (DMA_BASE+0x0100)   /* Channel 0 Mask register (RW,32,0x00000001) */
#define DMACTMOD0   (DMA_BASE+0x0104)   /* Channel 0 Transfer Mode register (RW,32,0x00000040) */
#define DMACSAD0    (DMA_BASE+0x0108)   /* Channel 0 Source Address register (RW,32,0x00000000) */
#define DMACDAD0    (DMA_BASE+0x010C)   /* Channel 0 Destination Address register (RW,32,0x00000000) */
#define DMACSIZ0    (DMA_BASE+0x0110)   /* Channel 0 Transfer Size register (RW,32,0x00000000) */
#define DMACCINT0   (DMA_BASE+0x0114)   /* Channel 0 interrupt Clear register (W,32,--) */
#define DMACMSK1    (DMA_BASE+0x0200)   /* Channel 1 Mask register (RW,32,0x00000001) */
#define DMACTMOD1   (DMA_BASE+0x0204)   /* Channel 1 Transfer Mode register (RW,32,0x00000040) */
#define DMACSAD1    (DMA_BASE+0x0208)   /* Channel 1 Source Address register (RW,32,0x00000000) */
#define DMACDAD1    (DMA_BASE+0x020C)   /* Channel 1 Destination Address register (RW,32,0x00000000) */
#define DMACSIZ1    (DMA_BASE+0x0210)   /* Channel 1 Transfer Size register (RW,32,0x00000000) */
#define DMACCINT1   (DMA_BASE+0x0214)   /* Channel 1 interrupt Clear register (W,32,--) */

/* bit field of DMAMOD register */
#define DMAMOD_PRI  (0x00000001)    /* PRI bit */
#define DMAMOD_FIX  (0x00000000)    /* Priority of DMA channel : CH0 > CH1 */
#define DMAMOD_RR   (0x00000001)    /* Priority of DMA channel : Round robin */

/* bit field of DMASTA register */
#define DMASTA_STA0 (0x00000001)    /* Non-transmitted data is in CH0 */
#define DMASTA_STA1 (0x00000002)    /* Non-transmitted data is in CH1 */

/* bit field of DMAINT register */
#define DMAINT_IREQ0    (0x00000001)    /* CH0 interrupt */
#define DMAINT_IREQ1    (0x00000002)    /* CH1 interrupt */
#define DMAINT_ISTA0    (0x00000100)    /* CH0 abnormal end */
#define DMAINT_ISTA1    (0x00000200)    /* CH1 abnormal end */
#define DMAINT_ISTP0    (0x00010000)    /* CH0 abnormal end situation */
#define DMAINT_ISTP1    (0x00020000)    /* CH1 abnormal end situation */

/* bit field of DMAMSK0,1 register */
#define DMACMSK_MSK (0x00000001)    /* Mask */

/* bit field of DMATMOD0,1 register */
#define DMACTMOD_ARQ    (0x00000001)    /* Auto request */
#define DMACTMOD_ERQ    (0x00000000)    /* External request */
#define DMACTMOD_BYTE   (0x00000000)    /* Byte transmission */
#define DMACTMOD_HWORD  (0x00000002)    /* Half word transmission */
#define DMACTMOD_WORD   (0x00000004)    /* Word transmission */
#define DMACTMOD_SFA    (0x00000000)    /* Source data type(fixed address device) */
#define DMACTMOD_SIA    (0x00000008)    /* Source data type(incremental address device) */
#define DMACTMOD_DFA    (0x00000000)    /* Destination data type(fixed address device) */
#define DMACTMOD_DIA    (0x00000010)    /* Destination data type(incremental address device) */
#define DMACTMOD_BM     (0x00000000)    /* Bus request mode(burst mode) */
#define DMACTMOD_CSM    (0x00000020)    /* Bus request mode(cycle steal mode) */
#define DMACTMOD_IMK    (0x00000040)    /* interrupt mask */


/*****************************************************/
/*    interrupt control register                     */
/*****************************************************/
#define EIC_BASE    (0x7BF00000)    /* base address */
#define IRCL        (EIC_BASE+0x04) /* Extended interrupt Clear register (W,32,--) */
#define IRQA        (EIC_BASE+0x10) /* Extended interrupt IRQ register (RW,32,0x00000000) */
#define IDM         (EIC_BASE+0x14) /* Extended interrupt Mode control register (RW,32,0x00000000) */
#define ILC         (EIC_BASE+0x18) /* Extended interrupt IRQ Level control register
                                       (RW,32,0x00000000) */

/* bit field of IRCL register */
#define IRCL_IRCL   (0x0000007F)    /* IRCL[6:0] */

/* bit field of IRQA register */
#define IRQA_IRQ16  (0x00000001)    /* IRQ16 */
#define IRQA_IRQ17  (0x00000002)    /* IRQ17 */
#define IRQA_IRQ18  (0x00000004)    /* IRQ18 */
#define IRQA_IRQ19  (0x00000008)    /* IRQ19 */
#define IRQA_IRQ20  (0x00000010)    /* IRQ20 */
#define IRQA_IRQ21  (0x00000020)    /* IRQ21 */
#define IRQA_IRQ22  (0x00000040)    /* IRQ22 */
#define IRQA_IRQ23  (0x00000080)    /* IRQ23 */
#define IRQA_IRQ24  (0x00000100)    /* IRQ24 */
#define IRQA_IRQ25  (0x00000200)    /* IRQ25 */
#define IRQA_IRQ26  (0x00000400)    /* IRQ26 */
#define IRQA_IRQ27  (0x00000800)    /* IRQ27 */
#define IRQA_IRQ28  (0x00001000)    /* IRQ28 */
#define IRQA_IRQ29  (0x00002000)    /* IRQ29 */
#define IRQA_IRQ30  (0x00004000)    /* IRQ30 */
#define IRQA_IRQ31  (0x00008000)    /* IRQ31 */

/* bit field of IDM register */
#define IDM_IDM22   (0x00000040)    /* IRQ22 */
#define IDM_IDM26   (0x00000400)    /* IRQ26 */
#define IDM_IDM28   (0x00001000)    /* IRQ28 */
#define IDM_IDM30   (0x00004000)    /* IRQ31 */
#define IDM_IDMP22  (0x00000080)    /* IRQ22 */
#define IDM_IDMP26  (0x00000800)    /* IRQ26 */
#define IDM_IDMP28  (0x00002000)    /* IRQ28 */
#define IDM_IDMP30  (0x00008000)    /* IRQ31 */
#define IDM_INT_L_L (0x00000000)    /* level sensing, interrupt occurs when 'L' */
#define IDM_INT_L_H (0x0000AAAA)    /* level sensing, interrupt occurs when 'H' */
#define IDM_INT_E_F (0x00005555)    /* edge sensing, interrupt occurs when falling edge */
#define IDM_INT_E_R (0x0000FFFF)    /* edge sensing, interrupt occurs when rising edge */
#define IDM_IRQ22   (0x000000C0)    /* IRQ22 */
#define IDM_IRQ26   (0x00000C00)    /* IRQ26 */
#define IDM_IRQ28   (0x00003000)    /* IRQ28 */
#define IDM_IRQ31   (0x0000C000)    /* IRQ31 */


/* bit field of ILC register */
#define ILC_INT_LV1 (0x11111111)    /* interrupt level 1 */
#define ILC_INT_LV2 (0x22222222)    /* interrupt level 2 */
#define ILC_INT_LV3 (0x33333333)    /* interrupt level 3 */
#define ILC_INT_LV4 (0x44444444)    /* interrupt level 4 */
#define ILC_INT_LV5 (0x55555555)    /* interrupt level 5 */
#define ILC_INT_LV6 (0x66666666)    /* interrupt level 6 */
#define ILC_INT_LV7 (0x77777777)    /* interrupt level 7 */
#define ILC_ILC16   (0x00000007)    /* IRQ16, IRQ17 */
#define ILC_ILC18   (0x00000070)    /* IRQ18, IRQ19 */
#define ILC_ILC20   (0x00000700)    /* IRQ20, IRQ21 */
#define ILC_ILC22   (0x00007000)    /* IRQ22, IRQ23 */
#define ILC_ILC24   (0x00070000)    /* IRQ24, IRQ25 */
#define ILC_ILC26   (0x00700000)    /* IRQ26, IRQ27 */
#define ILC_ILC28   (0x07000000)    /* IRQ28, IRQ29 */
#define ILC_ILC30   (0x70000000)    /* IRQ30, IRQ31 */


/*****************************************************/
/*    DRAM control register                          */
/*****************************************************/
#define DCR_BASE    (0x78180000)    /* base address */
#define DBWC        (DCR_BASE+0x00) /* DRAM Bus Width control register (RW,32,0x00000000) */
#define DRMC        (DCR_BASE+0x04) /* DRAM control register (RW,32,0x00000000) */
#define DRPC        (DCR_BASE+0x08) /* DRAM Attribute parameter Setup register (RW,32,0x00000000)*/
#define SDMD        (DCR_BASE+0x0C) /* SDRAM Mode Setup register (RW,32,0x00000001) */
#define DCMD        (DCR_BASE+0x10) /* DRAM Command register (RW,32,0x00000000) */
#define RFSH0       (DCR_BASE+0x14) /* DRAM Refresh Cycle register 0 (RW,32,0x00000000) */
#define PDWC        (DCR_BASE+0x18) /* Power Down Mode control register (RW,32,0x00000003) */
#define RFSH1       (DCR_BASE+0x1C) /* DRAM Refresh Cycle register 1 (RW,32,0x00000000) */