📄 intbvd1.c
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/*
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** Copyright 2000-2003 Intel Corporation All Rights Reserved.
**
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** related to the source code (Material) are owned by Intel Corporation
** or its suppliers or licensors. Title to the Material remains with
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** trade secrets and proprietary and confidential information of Intel
** or its suppliers and licensors. The Material is protected by worldwide
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** Material may be used, copied, reproduced, modified, published, uploaded,
** posted, transmitted, distributed, or disclosed in any way without Intel抯
** prior express written permission.
** No license under any patent, copyright, trade secret or other intellectual
** property right is granted to or conferred upon you by disclosure or
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*/
/*++
Module Name: $Workfile: intbvd1.c $
Abstract:
Intel XScale Microarchitecture platform interrupt service routine
for the Bulverde Mainstone plaform.
Notes:
Created: March 25, 2002
--*/
#include <windows.h>
#include <bldver.h>
#include <nkintr.h>
#include <oalintr.h>
#include "bvd1.h"
#include "bvd1BD.h"
#include "ISRDefs.h"
extern ReadICHP(void);
extern void WatchdogReset();
extern BOOL bWarmStart;
//
// Array of ISR functions
//
pFunc pIRQISR[MaxNumISRs] =
{
NoDefinedISR, // SSP3 - ID 0
NoDefinedISR, // Baseband - 1
USBNONOHCIISR, // USB Host Event - 2
USBOHCIISR, // OHCI - 3
KEYPADISR, // Keypad - 4
NoDefinedISR, // MEMstick - 5
NoDefinedISR, // Power I2C - 6
OSTM4_11TimerISR, // M4-M11 Timers - 7
#if 0 //hzh
#ifdef BSP_MAINSTONE
FPGAInterruptHandler, // GPIO0 edge detect - FPGA - 8
#else
NoDefinedISR, // GPIO0
#endif
GPIO1ISR, // GPIO1 edge detect - 9
NoDefinedISR, // GPIOxx_2 - 10
#else
GPIO1ISR, //use GPIO 0 as power button
GPIOInterruptHandler,
GPIOInterruptHandler,
#endif
UDCISR, // USB Client - 11
PMUISR, // PMU - 12
NoDefinedISR, // I2S - 13
NoDefinedISR, // AC97 - UCB1400
NoDefinedISR, // USIM - 15
NoDefinedISR, // SSP2 - 16
NoDefinedISR, // LCD controller - 17
NoDefinedISR, // I2C - 18
NoDefinedISR, // ICP - 19
STDUARTISR, // STD UART - 20
BTUARTISR, // BTUART - 21
FFUARTISR, // FFUART - 22
MMCISR, // MMC - 23
NoDefinedISR, // SSP1 - 24
DMACISR, // DMAC - 25
OSTM0TimerISR, // M0 - Scheduler - 26
OSTM1TimerISR, // M1 - Touch Timer - 27
OSTM2TimerISR, // M2 - Profiler - 28
OSTM3TimerISR, // M3 - 29
NoDefinedISR, // Hz Tick - 30
RTCAlarmISR, // RTC Alarm - 31
NoDefinedISR, // Trusted Platform Module
BvdCIISR // Bulverde Capture Interface
};
//
// OEMInterruptHandler
//
// IRQ interrupt routine.
//
// Read the IHCP register to get the highest priority
// interrupting device.
//
// Vector to the specific ISR routine.
//
// Inputs:
// ra - return address of the interrupted routine
//
int OEMInterruptHandler(unsigned int ra)
{
unsigned long devID,
ichp;
volatile BLR_REGS *v_pBLReg;
volatile XLLP_INTC_T *v_pICReg;
v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;
v_pBLReg = (volatile BLR_REGS *)FPGA_REGS_BASE_U_VIRTUAL;
//
// Ensure IRQ is valid
//
//ichp = ReadICHP();
ichp = v_pICReg->ichp;
// v_pBLReg->hex_led = ichp;
/*
#ifdef BSP_B0_BULVERDE
if (((ichp >> 16) & 0x00008000)==0)
#else
if ((ichp & 0x00008000)==0)
#endif
{
WRITE_HEX_LEDS (ichp);
lpWriteDebugStringFunc(TEXT("In OEMInterruptHandler - Invalid interrupt \r\n"));
return SYSINTR_NOP;
}
*/
if ( bWarmStart )
{
NKDbgPrintfW(TEXT("soft reset----\r\n"));
WatchdogReset();
}
//
// Get the priority of the interrupting device.
//
#ifdef BSP_B0_BULVERDE
devID = (ichp >> 16) & 0x0000003F;
#else
devID = ichp & 0x0000003F;
#endif
// WRITE_HEX_LEDS (devID);
//
// And execute its ISR
//
return(*pIRQISR[devID])(ra);
}
//
// Fast Interrupts - FIQs
//
// PMU may be our only FIQ interrupt.
//
void OEMInterruptHandlerFIQ(void)
{
}
//
// NoDefinedISR
//
// We get here on an undefined interrupt - the interrupt for
// the device is enabled, but no ISR defined.
//
static int NoDefinedISR (unsigned int ra)
{
unsigned long ichp;
volatile BLR_REGS *v_pBLReg;
v_pBLReg = (volatile BLR_REGS *)FPGA_REGS_BASE_U_VIRTUAL;
ichp = ReadICHP();
WRITE_HEX_LEDS (ichp);
lpWriteDebugStringFunc(TEXT("In NoDefinedISR \r\n"));
return SYSINTR_NOP;
}
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