sdconfig.h

YLP270的Windows CE5.0 bsp源码。

#undef USE_HW_OPTION
#define USE_HW_OPTION 1
#endif

/* CLOCK RATE definitions */
#define CLK_RATE_FULL           0x00    /* Master clock */
#define CLK_RATE_HALF           0x01    /* 1/2 Master clock */
#define CLK_RATE_FOUR           0x02    /* 1/4 Master clock */
#define CLK_RATE_EIGHT          0x03    /* 1/8 Master clock */
#define CLK_RATE_SIXTEEN        0x04    /* 1/16 Master clock */
#define CLK_RATE_THIRTY2        0x05    /* 1/32 Master clock */
#define CLK_RATE_SIXTY4         0x06    /* 1/64 Master clock */


#if (USE_MMC)

  #if (USE_MEMMODE)
    /* Processor memory base address */
    #define MMC_BASE_ADDR   0xFFF000

  #else

    /* MMC controller IO addresses */ 
        #define MMC_PRIMARY_IO_ADDRESS   0x278 
        #define MMC_SECONDARY_IO_ADDRESS 0x378
 
    #define SPDATA_REG      00
    #define SPSTAT_REG      01
    #define SPCTRL_REG      02
    #define EPPADDR_REG     03
    #define EPPDATA_REG     04


#define REV_NEW         0x310
#define REV_BORDER      0x301


#define RESP_FIFO_LENGTH        0x08


/* Register definitions */
#define STR_STP_CLK_REG         0x00    /* start stop clock */
#define STATUS_REG              0x02    /* Status */
#define CLK_RATE_REG            0x04    /* MMC Clock Rate */
#define REVISION_REG            0x06    /* Revision information */
#define SPI_REG                 0x08    /* SPI control */
#define CMD_DAT_CONT_REG        0x0A    /* Command data control */
#define RESPONSE_TOUT_REG       0x0C    /* Response time out */
#define READ_TOUT_REG           0x0E    /* Read time out */
#define BLK_LEN_REG             0x10    /* Block length register */
#define NOB_REG                 0x12    /* Number of blocks to transfer */
#define PWR_REG                 0x14    /* Power */
#define TEST_REG                0x16    /* Test */
#define TEST_CLK_COUNT_REG      0x18    /* Test Clock count */
#define INT_MASK_REG            0x1A    /* Interrupt Mask */
#define CMD_REG                 0x1C    /* Command Index */
#define ARGUMENT_HI_REG         0x1E    /* Argument High word */
#define ARGUMENT_LO_REG         0x20    /* Argument Low word */
#define RES_FIFO_REG            0x22    /* Response read address location */
#define FIFO_OE_REG             0x24    /* */
#define FIFO_RD_WR_REG          0x26    /* */
#define BUF_PART_FULL_REG       0x28    /* Buffer partial full */



/* START_STOP CLOCK register definitions */
#define STOP_CLOCK              0x01    /* Disable the clock */
#define START_CLOCK             0x02    /* Enable the clock */


/* STATUS register definitions (READ ONLY) */
#define TIME_OUT_RECEIVE        0x0001  /* TIME_OUT_RCVD - Time out receive data */
#define TIME_OUT_RESPONSE       0x0002  /* TIME_OUT_RES - Time out response */
#define CRC_WR_ERR              0x0004  /* CRC_WR_ERR - CRC write error */
#define CRC_RD_ERR              0x0008  /* CRC_RD_ERR - CRC read error */
#define ERR_CRC_NO_RESP         0x0010  /* ERR_CRC_NO_RESP - No response CRC */
#define RESP_CRC_ERR            0x0020  /* RESP_CRC_ERR - Response CRC error */
#define FIFO_BUFFER_EMPTY       0x0040  /* EFB - Empty fifo1 */
#define FIFO_BUFFER_FULL        0x0080  /* FFB - Full fifo1 */
#define CLOCK_ENABLE           0x0100  /* CLOCK_ENABLE - Clock enable */
#define RESERVE_EFB2            0x0200  /* EFB2 - Empty fifo2 */
#define RESERVE_FFB2            0x0400  /* FFB2 - Full fifo2 */
#define RD_DATA_AVAILABLE       0x0800  /* READ  -  Data available */
#define DONE_WDATA_XFER         0x0800  /* WRITE -  Finish WRITE request */
#define DONE_PROG_RDWR          0x1000  /* For write, End of programming data */
#define END_CMD_RES             0x2000  /* END_CMD_RES - End command response */
#define RESERVE_FIFO1_PAEN      0x4000  /* FIFO1_PAEN or FIFO1_PAFN */
#define RESERVE_FIFO2_PAEN      0x8000  /* FIFO2_PAEN or FIFO2_PAFN */


/* Interrupt Mask Definitions */
#define MASK_ON_TXFIFO_WR_REQ		(0x3F)
#define MASK_ON_RXFIFO_RD_REQ		(0x5F)
#define MASK_ON_PRG_DONE			(0x7D)
#define MASK_ON_DATA_TRAN_DONE		(0x7E)
#define MASK_OFF_ALL				(0x7F)




/* CMD_DAT_CONT register definitions */
#define RESPONSE_TYPE_R0        0x00
#define RESPONSE_TYPE_R1        0x01
#define RESPONSE_TYPE_R2        0x02
#define RESPONSE_TYPE_R3        0x03
#define DATA_ENABLE             0x04
#define DATA_READ_SET           0x00
#define DATA_WRITE_SET          0x08
#define DATA_STREAM_BLK         0x10
#define BUSY_SET                0x20
#define SEND_80_CLOCKS          0x40



/* Response Time Out register definitions */
#define DEFAULT_RESPONSE_TOUT   0xFF

/* Read Time Out Register definitions */
#define DEFAULT_READ_TOUT       0xFFFF

/* Block Length register definitions */
#define DEFAULT_BLK_LENGTH      0x200   /* 512-byte block length */

/* Number of Block register definition */
#define DEFAULT_NOB             0x01


/* Interrupt Mask Register definitions */
#define DATA_TRANSFER_INT       0x01
#define PROGPRAM_DONE_INT       0x02
#define CMD_RESPONSE_INT        0x04
#define BUFF_READY_INT          0x08


/* Buffer Partial Full register */
#define BUFF_PARTIAL_FULL       0x01


  #endif

 #endif         /* USE_MMC */

 
 

 #if (USE_INTERRUPTS)
    #define MMC_PRIMARY_INTERRUPT   IRQ_07 
    #define MMC_SECONDARY_INTERRUPT IRQ_05 
 #else
    #define MMC_PRIMARY_INTERRUPT   -1
    #define MMC_SECONDARY_INTERRUPT -1 
 #endif


#endif  /* (USE_MMC || USE_MMC_EMMULATION) */


/****************************** INTERRUPT VECTOR *****************************/
#define IRQ_15          0x0F    /* IRQ 15 */
#define IRQ_14          0x0E    /* IRQ 14 */
#define IRQ_12          0x0C    /* IRQ 12 */
#define IRQ_11          0x0B    /* IRQ 11 */
#define IRQ_10          0x0A    /* IRQ 10 */
#define IRQ_07          0x07    /* SPI, MMC IRQ7 */
#define IRQ_05          0x05    /* SPI, MMC IRQ5 */


/* Make sure number of controllers is selected */
#if (!N_CONTROLLERS)
error !!!!!  YOUR SETTING IS NOT CORRECTLY CONFIGURED  !!!!!
error -----   Please check your N_CONTROLLERS setting  -----
#endif

#if (!DRIVES_PER_CONTROLLER1 && !DRIVES_PER_CONTROLLER2)
error -----   Please check your DRIVES_PER_CONTROLLER setting  -----
#endif


/*========================= END TUNABLE CONSTANTS ===========================*/


/* ======================  PROCESSOR CONFIGURATION  ======================== */

/* This feature allows the processor that does not have byte accessing
*  capability, i.e. byte access is the same as word access. Byte access
*  is a 16-bit access.
*  The syntax is defined as follows:
*       CHAR_16BIT      1       Enable byte access as word access.
*       CHAR_16BIT      0       Disable byte access as word access.
*  This is a special case and handled by the File system.
*/
#define CHAR_16BIT      0


/* If set to 1 assume an intel byte ordering scheme. This eliminated 
* byte swapping and improves performance somewhat.
* If set to 0 bytes will be converted to big endian in appropriate
* places.
*/
#define LITTLE_ENDIAN  1

/* ====================  MEMORY MANAGEMENT METHODOLOGY  ==================== */

#ifdef __TURBOC__
#define SDFAR                  /* allocated in "far" memory. This is */ 
#else                           /* only relevent in intel small and   */ 

#ifdef _MSC_VER                 /* medium model code. */ 
#define SDFAR      
#else

#define SDFAR                     /* For other processors */
#endif

#endif

/* Always expect a large model pointer */
#if (WORD_ACCESS_ONLY)
  typedef unsigned short * USERADDRESS;
#else
  typedef unsigned char  * USERADDRESS;
#endif

typedef unsigned char   SDFAR *   FPTR;
typedef unsigned char   SDFAR *   FPTR08;
typedef unsigned short  SDFAR *   FPTR16;
typedef unsigned long   SDFAR *   FPTR32;


#if (CHAR_16BIT)
typedef unsigned short   UTINY;
typedef unsigned short   UTEXT;
typedef short            TEXT;
#define UTEXT_SIZE      1
#else
typedef unsigned char   UTINY;  /* unsigned 8 bit */
typedef unsigned char   UTEXT;  /* unsigned 8 bit for string */
typedef char            TEXT;   /* char for string */
#define UTEXT_SIZE      0
#endif



/* Error codes if an low level function fails. */
#define BUS_ERC_DIAG       101 /* Drive diagnostic failed in initialize */
#define BUS_ERC_ARGS       102 /* User supplied invalid arguments */
#define BUS_ERC_DRQ        103 /* DRQ should be asserted but it isn't
                  or driver and controller are out of phase*/
#define BUS_ERC_TIMEOUT    104 /* Timeout during some operation */
#define BUS_ERC_STATUS     105 /* Controller reported an error
                  look in the error register */
#define BUS_ERC_ADDR_RANGE 106 /* LBA out of range */
#define BUS_ERC_CNTRL_INIT 107 /* Fail to initialize controller_s structure */
#define BUS_ERC_IDDRV      108 /* Identify drive info error */
#define BUS_ERC_CMD_MULT   109 /* Read/Write Multiple Command attempts
                * to run before Set Multiple Command
                * has been executed */
#define BUS_ERC_BASE_ADDR  110 /* Base Address not Available */
#define BUS_ERC_CARD_ATA   111 /* Card is not ATA */



/* MMC completion code, the return value of most of the MMC driver fucntions */
typedef enum MMC_ERROR
{
    MMC_NO_ERROR = 0,               /* 0- Successful completion */
    MMC_CARD_IS_NOT_RESPONDING=201, /* 201- Time out error on card response */
    MMC_CMD_CRC_ERROR,              /* 202- CRC error detected on card response */
    MMC_DATA_CRC_ERROR,             /* 203- CRC error detected on incoming data block */
    MMC_DATA_STATUS_CRC_ERROR,      /* 204- Card is reporting CRC error on outgoing data block. */
    MMC_CARD_IS_BUSY,               /* 205- Card is busy programming */
    MMC_CARD_IS_NOT_READY,          /* 206- Card did not complete its initialization and is not ready. */
    MMC_COMUNC_CRC_ERROR,           /* 207- Card is reporting CRC error */
    MMC_COMUNC_ILLEG_COM,           /* 208- Card is reporting illegal command */
    MMC_ERASE_PARAM,                /* 209- Erase parameters error */
    MMC_WP_VIOLATION,               /* 210- Attempt to write a WP sector */
    MMC_ERROR,                      /* 211- MMC card internal error */
    MMC_WP_ERASE_SKIP,              /* 212- Attempt to erase WP sector */
    MMC_ADDRESS_ERROR,              /* 213- Sector messaligned error */
    MMC_CARD_READ_FAILURE,          /* 214- Card is reporting Read command failed */
    MMC_INTERFACE_ERROR,            /* 215- Error detected by the MMC HW driver */
    MMC_ILLEGAL_MODE,               /* 216- Not support in the current mode */
    MMC_COMMAND_PARAMETER_ERROR,    /* 217- Card is reporting Address-out-of-range error */
    MMC_ERASE_SEQ_ERROR,            /* 218- Error in the sequence of erase command */
    MMC_ERASE_RESET,                /* 219- Erase command canceled before execution */
    MMC_NO_CRC_STATUS,              /* 220- Time out on CRC status for Write */
    MMC_OVERRUN,                    /* 221- Overrun */
    MMC_UNDERRUN,                   /* 222- Underrun */
    MMC_CIDCSD_OVERWRITE,           /* 223- a) The CID register has been already */
                    /*        written and can be overwriten. */
                    /*     b) The read only section of CSD does not */
                    /*        match the card content. */
                    /*     c) An attempt to reverse the copy (set */
                    /*        as original) or permanent WP bits was made. */
    MMC_CARD_ECC_DISABLED,          /* 224- The command has been executed without */
                    /*     using the internal ECC. */
        MMC_READ_FOR_DATA,              /* 225- Corresponds to buffer empty signalling */
                    /*     on the bus. */
    MMC_DATA_LENGTH_ERROR,          /* 226- Data Length more then 512 bytes. */
    MMC_TIME_OUT_RCVD,              /* 227- Time out recive data (B0 for controller) */
    MMC_OUT_OF_RANGE,               /* 228- Address out of range error */
        MMC_CARD_ECC_FAILED,            /* 229- Internal Card ECC failed */
        MMC_CARD_IS_LOCKED,             /* 230- Card is locked by host */
        MMC_LOCK_UNLOCK_FAILED          /* 231- Lock/unlock card failed or access to locked card */
} MMC_CC;


#ifdef __cplusplus
}
#endif



#define __SDCONFIG__

#endif  /* SDCONFIG.H */