sdconfig.h

YLP270的Windows CE5.0 bsp源码。

/* In memory mapped mode,  a contiguous I/O register region is reffered in
** places where the alternate status register is accessed.
** It's convenient to use the contiguous I/O mode code.  Thus, enabling
** memory mode also turns on this one, but it has no other affects.
** This is the preferred choice and NOT intended to be CHANGED. 
*/
#if (USE_MEMMODE)
#undef USE_CONTIG_IO
/* Regardless the type of the peripheral buses,  when USE_MEMMODE
** is set to one,  USE_CONTIG_IO is always on to map ATA Task File Registers
** to 16-byte contiguous memory address spaces.
*/
#define USE_CONTIG_IO           1
#endif


/* Make sure one of the Peripheral Bus Interfaces is selected. */
#if (! (USE_SPI || USE_SPI_EMULATION || USE_MMC || USE_MMC_EMULATION) ) 
error Interface not defined.
#endif


#if (!USE_FILE_SYSTEM)
/* Since the low level storage driver does not have any restriction
** on writing,  the RTFS_WRITE option must always set when use without
** the FILE SYSTEM.
** This is NOT intended to be CHANGED. Otherwise, writing to the device
** is prohibited.
*/
#ifndef RTFS_WRITE
#define RTFS_WRITE      1
#endif
#endif


/* This option supports power management.
**      Set to 0 will cause the drive to go to sleep after 5ms of inactivity.
**      None zero value will be multiple of 5ms to stay in idle.
**      e.g. USE_PWR_MGMT 5  (device goes to sleep after 25ms of inactivity)
*/
#define USE_PWR_MGMT 0  /* Default of 5ms to go to sleep */


/*****************************************************************************/
/****************************** SPI SECTION **********************************/
/*****************************************************************************/

#if (USE_SPI || USE_SPI_EMULATION)

#if (!USE_HW_OPTION)
#undef USE_HW_OPTION
#define USE_HW_OPTION 1
#endif

/* CLOCK RATE definitions */
#define CLK_RATE_FULL           0x00    /* Master clock */
#define CLK_RATE_HALF           0x01    /* 1/2 Master clock */
#define CLK_RATE_FOUR           0x02    /* 1/4 Master clock */
#define CLK_RATE_EIGHT          0x03    /* 1/8 Master clock */
#define CLK_RATE_SIXTEEN        0x04    /* 1/16 Master clock */
#define CLK_RATE_THIRTY2        0x05    /* 1/32 Master clock */
#define CLK_RATE_SIXTY4         0x06    /* 1/64 Master clock */


/*********************************** NATIVE SPI ******************************/
 #if (USE_SPI)

  #if (USE_MEMMODE)
    /* 68328 Processor memory base address */
    #define SPI_BASE_ADDR   0xFFF000
    #define SPI_PRIMARY_MEM_ADDRESS         0x0
    #define SPI_SECONDARY_MEM_ADDRESS       0x0


    /* 68328 SPI Master control & Data registers */
    /* Offset from the Memory Base Address. */
    #define SPIM_OFF_DATAOUT 0x800   /* Master Data Out */
    #define SPIM_OFF_DATAIN 0x800   /* Master Data In */
    #define SPIM_OFF_CNTL   0x802
    #define SPIM_OFF_STAT   0x802

    /* Default value for SPI to control Speed, Bus Width, IRQ, Polarity,..*/
    #define SPI_CNTL_DEFAULT        0x6247


    /* SPI Control information */
    #define SPIM_IRQ_BIT    0x0080
    #define SPIM_IRQ_MASK   0xFF7F
    #define SPIM_XCH_BIT    0x0100  /* Transfer data bit */
    #define SPIM_XCH_MASK   0xFEFF
    #define SPIM_DEN_BIT    0x0200  /* Data Enable Bit */
    #define SPIM_DEN_MASK   0xFDFF


    /* Status information */
    #define SPIM_END_TRANSACTION    0x0080
    #define SPIM_XFER_ERRORS        0x0000  /* There is no error definition */
                        /* for the SPI master */


    /* Enable and Disable SPI Bus Master. These are used by the SPI driver. */
    /* Provide for 16-bit and 8-bit SPI bus per READ/WRITE ACCESS */

   #if (WORD_ACCESS_ONLY)
    /* Enable SPI Bus for 16-bit transaction */
    #define SPIM_ENABLE_BUS16       (SPI_CNTL_DEFAULT+8)
   #endif

    /* Enable SPI Bus for 8-bit transaction */
    #define SPIM_ENABLE_BUS8        SPI_CNTL_DEFAULT

    /* Disable SPI Bus */
    #define SPIM_DISABLE_BUS        (SPIM_DEN_MASK & SPIM_IRQ_MASK & SPIM_XCH_MASK)


    /* For SPI device Chip Select (CS should be low for the device to be active)*/
    #define SPIM_CS_MASK    0x08    /* For SPI device CS */
    #define SPIM_CS_REG     0x441


    /* 68328 Port K. Port K for SPI Master Configuration. */
    /* Offset from the Memory Base Address. */
    #define PK_OFF_DIR      0x440
    #define PK_OFF_DATA     0x441
    #define PK_OFF_PULLUP   0x442
    #define PK_OFF_SELECT   0x443


/* Block Length register definitions */
#define DEFAULT_BLK_LENGTH      0x200   /* 512-byte block length */
#define DATA_ENABLE             0x04
#define DATA_READ_SET           0x00
#define DATA_WRITE_SET          0x08
#define DATA_STREAM_BLK         0x10
#define BUSY_SET                0x20





  #else         /* IO MODE */

    /* SPI controller in IO mode */ 
    #define SPI_PRIMARY_IO_ADDRESS   0x170 
    #define SPI_SECONDARY_IO_ADDRESS 0x180


#define REV_NEW         0x310
#define REV_BORDER      0x301


#define RESP_FIFO_LENGTH        0x08


/* Register definitions */
#define STR_STP_CLK_REG         0x00    /* start stop clock */
#define STATUS_REG              0x02    /* Status */
#define CLK_RATE_REG            0x04    /* MMC Clock Rate */
#define REVISION_REG            0x06    /* Revision information */
#define SPI_REG                 0x08    /* SPI control */
#define CMD_DAT_CONT_REG        0x0A    /* Command data control */
#define RESPONSE_TOUT_REG       0x0C    /* Response time out */
#define READ_TOUT_REG           0x0E    /* Read time out */
#define BLK_LEN_REG             0x10    /* Block length register */
#define NOB_REG                 0x12    /* Number of blocks to transfer */
#define PWR_REG                 0x14    /* Power */
#define TEST_REG                0x16    /* Test */
#define TEST_CLK_COUNT_REG      0x18    /* Test Clock count */
#define INT_MASK_REG            0x1A    /* Interrupt Mask */
#define CMD_REG                 0x1C    /* Command Index */
#define ARGUMENT_HI_REG         0x1E    /* Argument High word */
#define ARGUMENT_LO_REG         0x20    /* Argument Low word */
#define RES_FIFO_REG            0x22    /* Response read address location */
#define FIFO_OE_REG             0x24    /* */
#define FIFO_RD_WR_REG          0x26    /* */
#define BUF_PART_FULL_REG       0x28    /* Buffer partial full */


/* START_STOP CLOCK register definitions */
#define STOP_CLOCK              0x01    /* Disable the clock */
#define START_CLOCK             0x02    /* Enable the clock */


/* STATUS register definitions (READ ONLY) */
#define TIME_OUT_RECEIVE        0x0001  /* TIME_OUT_RCVD - Time out receive data */
#define TIME_OUT_RESPONSE       0x0002  /* TIME_OUT_RES - Time out response */
#define CRC_WR_ERR              0x0004  /* CRC_WR_ERR - CRC write error */
#define CRC_RD_ERR              0x0008  /* CRC_RD_ERR - CRC read error */
#define ERR_CRC_NO_RESP         0x0010  /* ERR_CRC_NO_RESP - No response CRC */
#define RESP_CRC_ERR            0x0020  /* RESP_CRC_ERR - Response CRC error */
#define FIFO_BUFFER_EMPTY       0x0040  /* EFB - Empty fifo1 */
#define FIFO_BUFFER_FULL        0x0080  /* FFB - Full fifo1 */
#define CLOCK_ENABLE           0x0100  /* CLOCK_ENABLE - Clock enable */
#define RESERVE_EFB2            0x0200  /* EFB2 - Empty fifo2 */
#define RESERVE_FFB2            0x0400  /* FFB2 - Full fifo2 */
#define RD_DATA_AVAILABLE       0x0800  /* READ  -  Data available */
#define DONE_WDATA_XFER         0x0800  /* WRITE -  Finish WRITE request */
#define DONE_PROG_RDWR          0x1000  /* For write, End of programming data */
#define END_CMD_RES             0x2000  /* END_CMD_RES - End command response */
#define RESERVE_FIFO1_PAEN      0x4000  /* FIFO1_PAEN or FIFO1_PAFN */
#define RESERVE_FIFO2_PAEN      0x8000  /* FIFO2_PAEN or FIFO2_PAFN */

/* SPI register definitions */
#define SPI_ENABLE              0x01
#define SPI_CRC_ON              0x02
#define SPI_CS_ENABLE           0x04
/*
#define SPI_CS_ADDR0            0x08
#define SPI_CS_ADDR1            0x10
#define SPI_CS_ADDR2            0x18
#define SPI_CS_ADDR3            0x20
*/
#define SPI_CS_ADDR0            0x00
#define SPI_CS_ADDR1            0x08
#define SPI_CS_ADDR2            0x10
#define SPI_CS_ADDR3            0x18

/* CMD_DAT_CONT register definitions */
#define RESPONSE_TYPE_R0        0x00
#define RESPONSE_TYPE_R1        0x01
#define RESPONSE_TYPE_R2        0x02
#define RESPONSE_TYPE_R3        0x03
#define DATA_ENABLE             0x04
#define DATA_READ_SET           0x00
#define DATA_WRITE_SET          0x08
#define DATA_STREAM_BLK         0x10
#define BUSY_SET                0x20
#define SEND_80_CLOCKS          0x40
#define MMC_DMA_EN              0x80


/* Response Time Out register definitions */
#define DEFAULT_RESPONSE_TOUT   0xFF

/* Read Time Out Register definitions */
#define DEFAULT_READ_TOUT       0xFFFF

/* Block Length register definitions */
#define DEFAULT_BLK_LENGTH      0x200   /* 512-byte block length */

/* Number of Block register definition */
#define DEFAULT_NOB             0x01


/* Interrupt Mask Register definitions */
#define DATA_TRANSFER_INT       0x01
#define PROGPRAM_DONE_INT       0x02
#define CMD_RESPONSE_INT        0x04
#define BUFF_READY_INT          0x08


/* Buffer Partial Full register */
#define BUFF_PARTIAL_FULL       0x01


  #endif        /* USE_MEMMODE */
 
 #endif         /* USE_SPI */

/****************************** SPI EMULATION ********************************/
 #if (USE_SPI_EMULATION)
  
  #if (USE_MEMMODE)      
    /* Good for M32R processor serial emulation */ 
    #define SPI_BASE_ADDR   0xFF000000

    #define SPI_PRIMARY_MEM_ADDRESS  0x04400        /* Offset from base address */
    #define SPI_SECONDARY_IO_ADDRESS 0x00000

    #define SPICsio1Control    (SPI_PRIMARY_MEM_ADDRESS+0x00000001)
    #define SPICsio1Status     (SPI_PRIMARY_MEM_ADDRESS+0x00000003)
    #define SPICsio1TxData     (SPI_PRIMARY_MEM_ADDRESS+0x00000007)
    #define SPICsio1RxData     (SPI_PRIMARY_MEM_ADDRESS+0x00000009)
    #define SPICsio1IntMask    (SPI_PRIMARY_MEM_ADDRESS+0x0000000b)
    #define SPICsio1BaudRateCount      (SPI_PRIMARY_MEM_ADDRESS+0x0000000f)


    #define PORTJ_OFFSET    0x07000 /* Chip Select */
    #define CS_SERON        0x00    /* Turn on CS signal. Select the chip */
    #define CS_SEROFF       0x01    /* Turn off CS signal. Deselect the chip */

    #define PPort2          (PORTJ_OFFSET+0x00000003)
    #define PPort3          (PORTJ_OFFSET+0x00000009)

    #define PPortDir2       (PORTJ_OFFSET+0x00000006)
    #define PPortDir3       (PORTJ_OFFSET+0x0000000C)
  
  #else
    /* Good for SPI emulation of parallel controller */ 
    #define SPI_PRIMARY_IO_ADDRESS   0x378 
    #define SPI_SECONDARY_IO_ADDRESS 0x278

    #define PPDATA_REG      0x00
    #define PPCTRL_REG      0x02
    #define PPSTAT_REG      0x01

  #endif

 #endif  /* USE_SPI_EMULATION */

 #if (USE_INTERRUPTS)
    #define SPI_PRIMARY_INTERRUPT   IRQ_07 
    #define SPI_SECONDARY_INTERRUPT IRQ_05 
 #else
    #define SPI_PRIMARY_INTERRUPT   -1
    #define SPI_SECONDARY_INTERRUPT -1 
 #endif


#endif  /* USE_SPI || USE_SPI_EMULATION */


/*****************************************************************************/
/****************************** MMC SECTION **********************************/
/*****************************************************************************/

#if (USE_MMC || USE_MMC_EMULATION)

#if (!USE_HW_OPTION)