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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"    "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en"><head>	<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />	<style type="text/css">	body { font-family: Verdana, Arial, Helvetica, sans-serif;}	a.at-term {	font-style: italic; }	</style>	<title>General Considerations for MLP Programming</title>	<meta name="Generator" content="ATutor">	<meta name="Keywords" content=""></head><body> <h3>Amdahl's Law </h3>

<p>For our purposes, <em><a href="../glossary.html#Amdahl%27s+Law" target="body" class="at-term">Amdahl's Law</a></em> indicates that the speedup achievable through parallelization is limited by the portion of the serial code that cannot be 
parallelized. The paradigm we are discussing involves taking an existing MPI code and adding OpenMP directives to parallelize the computational work done by each MPI process. But, how much of the execution time of each MPI process can be parallelized using OpenMP? If this fraction is not high, then the overall speedup will be limited. </p>

<h3>Communication patterns </h3>

<p>How well do the application's communication needs match the underlying hardware? For codes in which pure MPI leads to rapid growth in communication traffic, a multilevel approach that limits the number of MPI processes may achieve better performance for larger number of processors. On clusters of SMPs pure MPI is typically better if the communications are latency dominated (i.e., for smaller 
message sizes), and worse if they are bandwidth dominated (for larger message sizes). </p>

<h3>Machine balance</h3>

<p>How are the CPUs, memory and interconnect performance related? Relative imbalances can increase (or decrease) the importance of communication costs, favoring one programming model over the another. For example, if the processors are relatively very fast compared to the interconnection network, applications will tend to be communication dominated. </p>

<h3>Memory access patterns </h3>

<p>Effective cache use is always important in achieving the best performance on microprocessor-based systems. It is especially so on systems where the intra-node memory bandwidth is limited. </p></body></html>

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