dds_sin.hier_info

用vhdl编写的程序

clk => acc1[10].CLK
clk => acc1[9].CLK
clk => acc1[8].CLK
clk => acc1[7].CLK
clk => acc1[6].CLK
clk => acc1[5].CLK
clk => acc1[4].CLK
clk => acc1[3].CLK
clk => acc1[2].CLK
clk => acc1[1].CLK
clk => acc1[0].CLK
clk => LPM_ROM:i_rom4.OUTCLOCK
clk => LPM_ROM:i_rom3.OUTCLOCK
clk => LPM_ROM:i_rom2.OUTCLOCK
clk => LPM_ROM:i_rom1.OUTCLOCK
clk => freqw[31].CLK
freqin[0] => freqw1[0].DATAIN
freqin[0] => freqw[0].DATAIN
freqin[1] => freqw1[1].DATAIN
freqin[1] => freqw[1].DATAIN
freqin[2] => freqw1[2].DATAIN
freqin[2] => freqw[2].DATAIN
freqin[3] => freqw1[3].DATAIN
freqin[3] => freqw[3].DATAIN
freqin[4] => freqw1[4].DATAIN
freqin[4] => freqw[4].DATAIN
freqin[5] => freqw1[5].DATAIN
freqin[5] => freqw[5].DATAIN
freqin[6] => freqw1[6].DATAIN
freqin[6] => freqw[6].DATAIN
freqin[7] => freqw1[7].DATAIN
freqin[7] => freqw[7].DATAIN
freqin[8] => freqw1[8].DATAIN
freqin[8] => freqw[8].DATAIN
freqin[9] => freqw1[9].DATAIN
freqin[9] => freqw[9].DATAIN
freqin[10] => freqw1[10].DATAIN
freqin[10] => freqw[10].DATAIN
freqin[11] => freqw1[11].DATAIN
freqin[11] => freqw[11].DATAIN
freqin[12] => freqw1[12].DATAIN
freqin[12] => freqw[12].DATAIN
freqin[13] => freqw1[13].DATAIN
freqin[13] => freqw[13].DATAIN
freqin[14] => freqw1[14].DATAIN
freqin[14] => freqw[14].DATAIN
freqin[15] => freqw1[15].DATAIN
freqin[15] => freqw[15].DATAIN
freqin[16] => freqw1[16].DATAIN
freqin[16] => freqw[16].DATAIN
freqin[17] => freqw1[17].DATAIN
freqin[17] => freqw[17].DATAIN
freqin[18] => freqw1[18].DATAIN
freqin[18] => freqw[18].DATAIN
freqin[19] => freqw1[19].DATAIN
freqin[19] => freqw[19].DATAIN
freqin[20] => freqw1[20].DATAIN
freqin[20] => freqw[20].DATAIN
freqin[21] => freqw1[21].DATAIN
freqin[21] => freqw[21].DATAIN
freqin[22] => freqw1[22].DATAIN
freqin[22] => freqw[22].DATAIN
freqin[23] => freqw1[23].DATAIN
freqin[23] => freqw[23].DATAIN
freqin[24] => freqw1[24].DATAIN
freqin[24] => freqw[24].DATAIN
freqin[25] => freqw1[25].DATAIN
freqin[25] => freqw[25].DATAIN
freqin[26] => freqw1[26].DATAIN
freqin[26] => freqw[26].DATAIN
freqin[27] => freqw1[27].DATAIN
freqin[27] => freqw[27].DATAIN
freqin[28] => freqw1[28].DATAIN
freqin[28] => freqw[28].DATAIN
freqin[29] => freqw1[29].DATAIN
freqin[29] => freqw[29].DATAIN
freqin[30] => freqw1[30].DATAIN
freqin[30] => freqw[30].DATAIN
freqin[31] => freqw[31].DATAIN
phasein[0] => phasew1[0].DATAIN
phasein[0] => phasew[0].DATAIN
phasein[1] => phasew1[1].DATAIN
phasein[1] => phasew[1].DATAIN
phasein[2] => phasew1[2].DATAIN
phasein[2] => phasew[2].DATAIN
phasein[3] => phasew1[3].DATAIN
phasein[3] => phasew[3].DATAIN
phasein[4] => phasew1[4].DATAIN
phasein[4] => phasew[4].DATAIN
phasein[5] => phasew1[5].DATAIN
phasein[5] => phasew[5].DATAIN
phasein[6] => phasew1[6].DATAIN
phasein[6] => phasew[6].DATAIN
phasein[7] => phasew1[7].DATAIN
phasein[7] => phasew[7].DATAIN
phasein[8] => phasew1[8].DATAIN
phasein[8] => phasew[8].DATAIN
phasein[9] => phasew1[9].DATAIN
phasein[9] => phasew[9].DATAIN
phasein[10] => phasew1[10].DATAIN
phasein[10] => phasew[10].DATAIN
phasein[11] => phasew1[11].DATAIN
phasein[11] => phasew[11].DATAIN
phasein[12] => phasew1[12].DATAIN
phasein[12] => phasew[12].DATAIN
phasein[13] => phasew1[13].DATAIN
phasein[13] => phasew[13].DATAIN
phasein[14] => phasew1[14].DATAIN
phasein[14] => phasew[14].DATAIN
phasein[15] => phasew1[15].DATAIN
phasein[15] => phasew[15].DATAIN
ddsout[0] <= ddsout~29.DB_MAX_OUTPUT_PORT_TYPE
ddsout[1] <= ddsout~28.DB_MAX_OUTPUT_PORT_TYPE
ddsout[2] <= ddsout~27.DB_MAX_OUTPUT_PORT_TYPE
ddsout[3] <= ddsout~26.DB_MAX_OUTPUT_PORT_TYPE
ddsout[4] <= ddsout~25.DB_MAX_OUTPUT_PORT_TYPE
ddsout[5] <= ddsout~24.DB_MAX_OUTPUT_PORT_TYPE
ddsout[6] <= ddsout~23.DB_MAX_OUTPUT_PORT_TYPE
ddsout[7] <= ddsout~22.DB_MAX_OUTPUT_PORT_TYPE
ddsout[8] <= ddsout~21.DB_MAX_OUTPUT_PORT_TYPE
ddsout[9] <= ddsout~20.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[0] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[1] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[2] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[3] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[4] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[5] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[6] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[7] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[8] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
ddsout145[9] <= add~7.DB_MAX_OUTPUT_PORT_TYPE
SEL[0] => Equal~3.IN3
SEL[0] => Equal~4.IN3
SEL[0] => Equal~5.IN3
SEL[1] => Equal~3.IN2
SEL[1] => Equal~4.IN2
SEL[1] => Equal~5.IN2
aa => aacnt1[2].CLK
aa => aacnt1[1].CLK
aa => aacnt1[0].CLK
aa => aacnt1[3].CLK
bb => bbcnt1[2].CLK
bb => bbcnt1[1].CLK
bb => bbcnt1[0].CLK
bb => bbcnt1[3].CLK
cc => cccnt1[2].CLK
cc => cccnt1[1].CLK
cc => cccnt1[0].CLK
cc => cccnt1[3].CLK
aacnt[0] <= aacnt1[0].DB_MAX_OUTPUT_PORT_TYPE
aacnt[1] <= aacnt1[1].DB_MAX_OUTPUT_PORT_TYPE
aacnt[2] <= aacnt1[2].DB_MAX_OUTPUT_PORT_TYPE
aacnt[3] <= aacnt1[3].DB_MAX_OUTPUT_PORT_TYPE
bbcnt[0] <= bbcnt1[0].DB_MAX_OUTPUT_PORT_TYPE
bbcnt[1] <= bbcnt1[1].DB_MAX_OUTPUT_PORT_TYPE
bbcnt[2] <= bbcnt1[2].DB_MAX_OUTPUT_PORT_TYPE
bbcnt[3] <= bbcnt1[3].DB_MAX_OUTPUT_PORT_TYPE
cccnt[0] <= cccnt1[0].DB_MAX_OUTPUT_PORT_TYPE
cccnt[1] <= cccnt1[1].DB_MAX_OUTPUT_PORT_TYPE
cccnt[2] <= cccnt1[2].DB_MAX_OUTPUT_PORT_TYPE
cccnt[3] <= cccnt1[3].DB_MAX_OUTPUT_PORT_TYPE
ddsout11[0] <= LPM_ROM:i_rom1.Q[0]
ddsout11[1] <= LPM_ROM:i_rom1.Q[1]
ddsout11[2] <= LPM_ROM:i_rom1.Q[2]
ddsout11[3] <= LPM_ROM:i_rom1.Q[3]
ddsout11[4] <= LPM_ROM:i_rom1.Q[4]
ddsout11[5] <= LPM_ROM:i_rom1.Q[5]
ddsout11[6] <= LPM_ROM:i_rom1.Q[6]
ddsout11[7] <= LPM_ROM:i_rom1.Q[7]
ddsout11[8] <= LPM_ROM:i_rom1.Q[8]
ddsout11[9] <= LPM_ROM:i_rom1.Q[9]
ddsout22[0] <= LPM_ROM:i_rom2.Q[0]
ddsout22[1] <= LPM_ROM:i_rom2.Q[1]
ddsout22[2] <= LPM_ROM:i_rom2.Q[2]
ddsout22[3] <= LPM_ROM:i_rom2.Q[3]
ddsout22[4] <= LPM_ROM:i_rom2.Q[4]
ddsout22[5] <= LPM_ROM:i_rom2.Q[5]
ddsout22[6] <= LPM_ROM:i_rom2.Q[6]
ddsout22[7] <= LPM_ROM:i_rom2.Q[7]
ddsout22[8] <= LPM_ROM:i_rom2.Q[8]
ddsout22[9] <= LPM_ROM:i_rom2.Q[9]
ddsout33[0] <= LPM_ROM:i_rom3.Q[0]
ddsout33[1] <= LPM_ROM:i_rom3.Q[1]
ddsout33[2] <= LPM_ROM:i_rom3.Q[2]
ddsout33[3] <= LPM_ROM:i_rom3.Q[3]
ddsout33[4] <= LPM_ROM:i_rom3.Q[4]
ddsout33[5] <= LPM_ROM:i_rom3.Q[5]
ddsout33[6] <= LPM_ROM:i_rom3.Q[6]
ddsout33[7] <= LPM_ROM:i_rom3.Q[7]
ddsout33[8] <= LPM_ROM:i_rom3.Q[8]
ddsout33[9] <= LPM_ROM:i_rom3.Q[9]
romaddr_back[0] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[1] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[2] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[3] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[4] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[5] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[6] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[7] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[8] <= add~5.DB_MAX_OUTPUT_PORT_TYPE
romaddr_back[9] <= add~5.DB_MAX_OUTPUT_PORT_TYPE


|dds_sin|ddsc:i_dds|LPM_ROM:i_rom1
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => ~NO_FANOUT~
outclock => altrom:srom.clocko
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE


|dds_sin|ddsc:i_dds|LPM_ROM:i_rom1|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
address[6] => altsyncram:rom_block.address_a[6]
address[7] => altsyncram:rom_block.address_a[7]
address[8] => altsyncram:rom_block.address_a[8]
address[9] => altsyncram:rom_block.address_a[9]
clocki => ~NO_FANOUT~
clocko => altsyncram:rom_block.clock0
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]
q[7] <= altsyncram:rom_block.q_a[7]
q[8] <= altsyncram:rom_block.q_a[8]
q[9] <= altsyncram:rom_block.q_a[9]


|dds_sin|ddsc:i_dds|LPM_ROM:i_rom1|altrom:srom|altsyncram:rom_block
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_jqo:auto_generated.address_a[0]
address_a[1] => altsyncram_jqo:auto_generated.address_a[1]
address_a[2] => altsyncram_jqo:auto_generated.address_a[2]
address_a[3] => altsyncram_jqo:auto_generated.address_a[3]
address_a[4] => altsyncram_jqo:auto_generated.address_a[4]
address_a[5] => altsyncram_jqo:auto_generated.address_a[5]
address_a[6] => altsyncram_jqo:auto_generated.address_a[6]
address_a[7] => altsyncram_jqo:auto_generated.address_a[7]
address_a[8] => altsyncram_jqo:auto_generated.address_a[8]
address_a[9] => altsyncram_jqo:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_jqo:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_jqo:auto_generated.q_a[0]
q_a[1] <= altsyncram_jqo:auto_generated.q_a[1]
q_a[2] <= altsyncram_jqo:auto_generated.q_a[2]
q_a[3] <= altsyncram_jqo:auto_generated.q_a[3]
q_a[4] <= altsyncram_jqo:auto_generated.q_a[4]
q_a[5] <= altsyncram_jqo:auto_generated.q_a[5]
q_a[6] <= altsyncram_jqo:auto_generated.q_a[6]
q_a[7] <= altsyncram_jqo:auto_generated.q_a[7]
q_a[8] <= altsyncram_jqo:auto_generated.q_a[8]
q_a[9] <= altsyncram_jqo:auto_generated.q_a[9]
q_b[0] <= <GND>


|dds_sin|ddsc:i_dds|LPM_ROM:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5