alt_u_div_jod.tdf

用vhdl编写的程序

--alt_u_div DEVICE_FAMILY="Cyclone" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 WIDTH_D=6 WIDTH_N=16 WIDTH_Q=16 WIDTH_R=6 denominator numerator quotient remainder
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_abs 2005:08:17:17:24:32:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_divide 2005:03:24:20:40:32:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


--  Copyright (C) 1991-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION add_sub_ke8 (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_le8 (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);
FUNCTION add_sub_qe8 (dataa[6..0], datab[6..0])
RETURNS ( cout, result[6..0]);
FUNCTION add_sub_me8 (dataa[2..0], datab[2..0])
RETURNS ( cout, result[2..0]);
FUNCTION add_sub_ne8 (dataa[3..0], datab[3..0])
RETURNS ( cout, result[3..0]);
FUNCTION add_sub_oe8 (dataa[4..0], datab[4..0])
RETURNS ( cout, result[4..0]);
FUNCTION add_sub_pe8 (dataa[5..0], datab[5..0])
RETURNS ( cout, result[5..0]);

--synthesis_resources = lut 25 
SUBDESIGN alt_u_div_jod
( 
	den_out[5..0]	:	output;
	denominator[5..0]	:	input;
	numerator[15..0]	:	input;
	quotient[15..0]	:	output;
	remainder[5..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_ke8;
	add_sub_1 : add_sub_le8;
	add_sub_10 : add_sub_qe8;
	add_sub_11 : add_sub_qe8;
	add_sub_12 : add_sub_qe8;
	add_sub_13 : add_sub_qe8;
	add_sub_14 : add_sub_qe8;
	add_sub_15 : add_sub_qe8;
	add_sub_2 : add_sub_me8;
	add_sub_3 : add_sub_ne8;
	add_sub_4 : add_sub_oe8;
	add_sub_5 : add_sub_pe8;
	add_sub_6 : add_sub_qe8;
	add_sub_7 : add_sub_qe8;
	add_sub_8 : add_sub_qe8;
	add_sub_9 : add_sub_qe8;
	DenominatorIn[118..0]	: WIRE;
	DenominatorIn_tmp[118..0]	: WIRE;
	gnd_wire	: WIRE;