dds_sin.fit.qmsg

用vhdl编写的程序

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "sysclk " "Info: Promoted signal \"sysclk\" to use global clock" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sysclk" } { 0 "sysclk" } } } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 7 -1 0 } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { sysclk } "NODE_NAME" } "" } } { "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" { Floorplan "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" "" { sysclk } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "ppl2_5:ppl\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"ppl2_5:ppl\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ppl2_5:ppl\|altpll:altpll_component\|_clk0" } { 0 "ppl2_5:ppl\|altpll:altpll_component\|_clk0" } } } } { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 114 -1 0 } } { "altpll.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { ppl2_5:ppl|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" { Floorplan "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" "" { ppl2_5:ppl|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "ddsc:i_dds\|acc\[22\] Global clock " "Info: Automatically promoted some destinations of signal \"ddsc:i_dds\|acc\[22\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a0 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a0\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a1 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a1\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a2 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a2\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a3 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a3\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a4 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a4\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a5 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a5\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a6 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a6\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a7 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a7\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a8 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a8\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a9 " "Info: Destination \"ddsc:i_dds\|lpm_rom:i_rom3\|altrom:srom\|altsyncram:rom_block\|altsyncram_t0p:auto_generated\|ram_block1a9\" may be non-global or may not use global clock" {  } { { "db/altsyncram_t0p.tdf" "" { Text "D:/VHDL/copy/dds_sin_std4/db/altsyncram_t0p.tdf" 40 2 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "ddsc.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/ddsc.vhd" 96 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "amp Global clock " "Info: Automatically promoted signal \"amp\" to use Global clock" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 22 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "amp " "Info: Pin \"amp\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 22 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "amp" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { amp } "NODE_NAME" } "" } } { "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" { Floorplan "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" "" { amp } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "aa Global clock " "Info: Automatically promoted signal \"aa\" to use Global clock" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 20 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "aa " "Info: Pin \"aa\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 20 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "aa" } } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dds_sin" "UNKNOWN" "V1" "D:/VHDL/copy/dds_sin_std4/db/dds_sin.quartus_db" { Floorplan "D:/VHDL/copy/dds_sin_std4/" "" "" { aa } "NODE_NAME" } "" } } { "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" { Floorplan "D:/VHDL/copy/dds_sin_std4/dds_sin.fld" "" "" { aa } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "bb Global clock " "Info: Automatically promoted signal \"bb\" to use Global clock" {  } { { "dds_sin.vhd" "" { Text "D:/VHDL/copy/dds_sin_std4/dds_sin.vhd" 20 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}