dds_sin.map.rpt

用vhdl编写的程序

Analysis & Synthesis report for dds_sin
Tue Sep 12 15:10:13 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Source assignments for ddsc:i_dds|LPM_ROM:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated
 11. Source assignments for ddsc:i_dds|LPM_ROM:i_rom2|altrom:srom|altsyncram:rom_block|altsyncram_5to:auto_generated
 12. Source assignments for ddsc:i_dds|LPM_ROM:i_rom3|altrom:srom|altsyncram:rom_block|altsyncram_t0p:auto_generated
 13. Source assignments for ddsc:i_dds|LPM_ROM:i_rom4|altrom:srom|altsyncram:rom_block|altsyncram_4so:auto_generated
 14. Source assignments for myram:ram|altsyncram:altsyncram_component|altsyncram_qod1:auto_generated
 15. Parameter Settings for User Entity Instance: ppl2_5:ppl|altpll:altpll_component
 16. Parameter Settings for User Entity Instance: ddsc:i_dds
 17. Parameter Settings for User Entity Instance: ddsc:i_dds|LPM_ROM:i_rom1
 18. Parameter Settings for User Entity Instance: ddsc:i_dds|LPM_ROM:i_rom2
 19. Parameter Settings for User Entity Instance: ddsc:i_dds|LPM_ROM:i_rom3
 20. Parameter Settings for User Entity Instance: ddsc:i_dds|LPM_ROM:i_rom4
 21. Parameter Settings for User Entity Instance: mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component
 22. Parameter Settings for User Entity Instance: mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_mult:mac_mult1
 23. Parameter Settings for User Entity Instance: mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_mult:mac_mult2
 24. Parameter Settings for User Entity Instance: mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_mult:mac_mult3
 25. Parameter Settings for User Entity Instance: mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4
 26. Parameter Settings for User Entity Instance: mul_6:mul|ll:u2|lpm_divide:lpm_divide_component
 27. Parameter Settings for User Entity Instance: myram:ram|altsyncram:altsyncram_component
 28. altmult_add Parameter Settings by Entity Instance
 29. Analysis & Synthesis Equations
 30. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 12 15:10:12 2006    ;
; Quartus II Version          ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name               ; dds_sin                                  ;
; Top-level Entity Name       ; dds_sin                                  ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 596                                      ;
; Total pins                  ; 48                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 51,200                                   ;
; Total PLLs                  ; 1                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1C3T144C8        ;                    ;
; Top-level entity name                                              ; dds_sin            ; dds_sin            ;
; Family name                                                        ; Cyclone            ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;