dds_sin.tan.summary

用vhdl编写的程序

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.460 ns
From           : sel[0]
To             : freqind[17]
From Clock     : --
To Clock       : sysclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.407 ns
From           : count[5]
To             : amp_out[5]
From Clock     : amp
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 5.013 ns
From           : sysclk
To             : dclk
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.395 ns
From           : RD
To             : DIN[5]
From Clock     : --
To Clock       : sysclk
Failed Paths   : 0

Type           : Clock Setup: 'sysclk'
Slack          : -9.605 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|ram_block1a1~porta_address_reg9
To             : ddsout_rom[8]
From Clock     : ppl2_5:ppl|altpll:altpll_component|_clk0
To Clock       : sysclk
Failed Paths   : 1134

Type           : Clock Setup: 'ppl2_5:ppl|altpll:altpll_component|_clk0'
Slack          : -0.244 ns
Required Time  : 250.00 MHz ( period = 4.000 ns )
Actual Time    : 235.63 MHz ( period = 4.244 ns )
From           : QRD[3]
To             : QRD[0]
From Clock     : ppl2_5:ppl|altpll:altpll_component|_clk0
To Clock       : ppl2_5:ppl|altpll:altpll_component|_clk0
Failed Paths   : 30

Type           : Clock Setup: 'cc'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : ddsc:i_dds|cccnt1[1]
To             : ddsc:i_dds|cccnt1[3]
From Clock     : cc
To Clock       : cc
Failed Paths   : 0

Type           : Clock Setup: 'aa'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : ddsc:i_dds|aacnt1[0]
To             : ddsc:i_dds|aacnt1[1]
From Clock     : aa
To Clock       : aa
Failed Paths   : 0

Type           : Clock Setup: 'bb'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : ddsc:i_dds|bbcnt1[2]
To             : ddsc:i_dds|bbcnt1[3]
From Clock     : bb
To Clock       : bb
Failed Paths   : 0

Type           : Clock Setup: 'amp'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : count[1]
To             : count[5]
From Clock     : amp
To Clock       : amp
Failed Paths   : 0

Type           : Clock Hold: 'ppl2_5:ppl|altpll:altpll_component|_clk0'
Slack          : -0.786 ns
Required Time  : 250.00 MHz ( period = 4.000 ns )
Actual Time    : N/A
From           : ddsout_rom[3]
To             : DIN[3]
From Clock     : sysclk
To Clock       : ppl2_5:ppl|altpll:altpll_component|_clk0
Failed Paths   : 5

Type           : Clock Hold: 'sysclk'
Slack          : 1.787 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_mult:mac_mult1|dataa_n[1]
To             : mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_mult:mac_mult1|dataout_n[0]
From Clock     : sysclk
To Clock       : sysclk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1169

--------------------------------------------------------------------------------------