dds_sin.map.eqn

用vhdl编写的程序

--T1L25 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[13]~143
--operation mode is arithmetic

T1L25 = CARRY(X2_result[13] & !X1_result[13] & !T1L23 # !X2_result[13] & (!T1L23 # !X1_result[13]));


--NB7_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_6|add_sub_cella[4]
--operation mode is arithmetic

NB7_add_sub_cella[4] = T1_dataout_n[13];

--NB7L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_6|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB7L5 = CARRY(T1_dataout_n[13]);


--T1_dataout_n[14] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14]
--operation mode is arithmetic

T1_dataout_n[14]_carry_eqn = T1L25;
T1_dataout_n[14]_lut_out = X1_result[14] $ (!T1_dataout_n[14]_carry_eqn);
T1_dataout_n[14] = DFFEAS(T1_dataout_n[14]_lut_out, sysclk, VCC, , , , , , );

--T1L27 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14]~147
--operation mode is arithmetic

T1L27 = CARRY(X1_result[14] & (!T1L25));


--MB1_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]
--operation mode is arithmetic

MB1_add_sub_cella[4] = T1_dataout_n[14];

--MB1L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~COUT
--operation mode is arithmetic

MB1L5 = CARRY(T1_dataout_n[14]);


--T1_dataout_n[15] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[15]
--operation mode is normal

T1_dataout_n[15]_carry_eqn = T1L27;
T1_dataout_n[15]_lut_out = T1_dataout_n[15]_carry_eqn;
T1_dataout_n[15] = DFFEAS(T1_dataout_n[15]_lut_out, sysclk, VCC, , , , , , );


--LB1_cout is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_oe8:add_sub_4|cout
--operation mode is arithmetic

LB1_cout = CARRY(T1_dataout_n[15]);


--MB1L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[5]~71
--operation mode is normal

MB1L6_carry_eqn = LB1_cout;
MB1L6 = T1_dataout_n[15] & (!MB1L6_carry_eqn);


--FB1L1 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[39]~1021
--operation mode is normal

FB1L1 = MB1L4 & (!MB1_add_sub_cella[4]) # !MB1L4 & (MB1L6 & (!MB1_add_sub_cella[4]) # !MB1L6 & T1_dataout_n[14]);


--FB1L2 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1022
--operation mode is normal

FB1L2 = NB7L4 # FB1L1 # MB1L4 & MB1L6;


--FB1L3 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1023
--operation mode is normal

FB1L3 = FB1L2 & (!NB7_add_sub_cella[4]) # !FB1L2 & T1_dataout_n[13];


--NB8L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[5]~141
--operation mode is normal

NB8L6 = NB7L4 & FB1L1 # !NB7L4 & !FB1L1 & MB1L4 & MB1L6;


--NB8L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[5]~142
--operation mode is normal

NB8L7 = NB8L4 # FB1L3 # NB8L6;


--FB1L4 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[53]~1024
--operation mode is normal

FB1L4 = NB8L7 & (!NB8_add_sub_cella[4]) # !NB8L7 & T1_dataout_n[12];


--NB9L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[5]~185
--operation mode is normal

NB9L6 = NB8L4 & FB1L3 # !NB8L4 & !FB1L3 & NB8L6;


--NB9L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[5]~186
--operation mode is normal

NB9L7 = NB9L4 # FB1L4 # NB9L6;


--T1_dataout_n[11] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[11]
--operation mode is arithmetic

T1_dataout_n[11]_carry_eqn = T1L19;
T1_dataout_n[11]_lut_out = X2_result[11] $ X1_result[11] $ T1_dataout_n[11]_carry_eqn;
T1_dataout_n[11] = DFFEAS(T1_dataout_n[11]_lut_out, sysclk, VCC, , , , , , );

--T1L21 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[11]~155
--operation mode is arithmetic

T1L21 = CARRY(X2_result[11] & !X1_result[11] & !T1L19 # !X2_result[11] & (!T1L19 # !X1_result[11]));


--NB10_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_9|add_sub_cella[4]
--operation mode is arithmetic

NB10_add_sub_cella[4] = T1_dataout_n[10];

--NB10L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_9|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB10L5 = CARRY(T1_dataout_n[10]);


--NB1L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~86
--operation mode is normal

NB1L6 = !NB10L4 & (NB9L7 & NB9_add_sub_cella[4] # !NB9L7 & (!T1_dataout_n[11]));


--NB10L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_9|add_sub_cella[5]~84
--operation mode is normal

NB10L6 = NB9L4 & FB1L4 # !NB9L4 & !FB1L4 & NB9L6;


--FB1L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[67]~1025
--operation mode is normal

FB1L6 = NB1L6 & (NB10L6 & (!NB10_add_sub_cella[4]) # !NB10L6 & T1_dataout_n[10]) # !NB1L6 & (!NB10_add_sub_cella[4]);


--FB1L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[60]~1026
--operation mode is normal

FB1L5 = NB9L7 & (!NB9_add_sub_cella[4]) # !NB9L7 & T1_dataout_n[11];


--NB1L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~87
--operation mode is normal

NB1L7 = NB10L4 & FB1L5 # !NB10L4 & !FB1L5 & NB10L6;


--NB1L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~88
--operation mode is normal

NB1L8 = NB1L4 # FB1L6 # NB1L7;


--FB1L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[74]~1027
--operation mode is normal

FB1L7 = NB1L8 & (!NB1_add_sub_cella[4]) # !NB1L8 & T1_dataout_n[9];


--NB2L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[5]~84
--operation mode is normal

NB2L6 = NB1L4 & FB1L6 # !NB1L4 & !FB1L6 & NB1L7;


--NB2L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[5]~85
--operation mode is normal

NB2L7 = NB2L4 # FB1L7 # NB2L6;


--FB1L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[81]~1028
--operation mode is normal

FB1L8 = NB2L7 & (!NB2_add_sub_cella[4]) # !NB2L7 & T1_dataout_n[8];


--NB3L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[5]~84
--operation mode is normal

NB3L6 = NB2L4 & FB1L7 # !NB2L4 & !FB1L7 & NB2L6;


--NB3L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[5]~85
--operation mode is normal

NB3L7 = NB3L4 # FB1L8 # NB3L6;


--T1_dataout_n[7] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7]
--operation mode is arithmetic

T1_dataout_n[7]_carry_eqn = T1L11;
T1_dataout_n[7]_lut_out = X2_result[7] $ X1_result[7] $ T1_dataout_n[7]_carry_eqn;
T1_dataout_n[7] = DFFEAS(T1_dataout_n[7]_lut_out, sysclk, VCC, , , , , , );

--T1L13 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7]~159
--operation mode is arithmetic

T1L13 = CARRY(X2_result[7] & !X1_result[7] & !T1L11 # !X2_result[7] & (!T1L11 # !X1_result[7]));


--NB4_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]
--operation mode is arithmetic

NB4_add_sub_cella[4] = T1_dataout_n[6];

--NB4L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]~COUT
--operation mode is arithmetic

NB4L5 = CARRY(T1_dataout_n[6]);


--NB5L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~103
--operation mode is normal

NB5L6 = !NB4L4 & (NB3L7 & NB3_add_sub_cella[4] # !NB3L7 & (!T1_dataout_n[7]));


--NB4L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[5]~86
--operation mode is normal

NB4L6 = NB3L4 & FB1L8 # !NB3L4 & !FB1L8 & NB3L6;


--FB1L10 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~1029
--operation mode is normal

FB1L10 = NB5L6 & (NB4L6 & (!NB4_add_sub_cella[4]) # !NB4L6 & T1_dataout_n[6]) # !NB5L6 & (!NB4_add_sub_cella[4]);


--A1L67 is ddsout_rom~763
--operation mode is normal

A1L67 = !NB5L4 & !FB1L10 # !NB5_add_sub_cella[4];


--T1_dataout_n[5] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[5]
--operation mode is arithmetic

T1_dataout_n[5]_carry_eqn = T1L3;
T1_dataout_n[5]_lut_out = X2_result[5] $ X1_result[5] $ T1_dataout_n[5]_carry_eqn;
T1_dataout_n[5] = DFFEAS(T1_dataout_n[5]_lut_out, sysclk, VCC, , , , , , );

--T1L9 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[5]~163
--operation mode is arithmetic

T1L9 = CARRY(X2_result[5] & !X1_result[5] & !T1L3 # !X2_result[5] & (!T1L3 # !X1_result[5]));


--FB1L9 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[88]~1030
--operation mode is normal

FB1L9 = NB3L7 & (!NB3_add_sub_cella[4]) # !NB3L7 & T1_dataout_n[7];