dds_sin.fit.eqn

用vhdl编写的程序

NB9L7 = NB8L4 & (FB1L3) # !NB8L4 & (NB8L7 & !FB1L3);


--NB9L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[5]~186 at LC_X20_Y6_N5
--operation mode is normal

NB9L8 = NB9L4 # NB9L7 # FB1L4;


--T1_dataout_n[11] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[11] at LC_X19_Y3_N3
--operation mode is arithmetic

T1_dataout_n[11]_carry_eqn = (!T1L22 & T1L30) # (T1L22 & T1L31);
T1_dataout_n[11]_lut_out = X1_result[11] $ X2_result[11] $ T1_dataout_n[11]_carry_eqn;
T1_dataout_n[11] = DFFEAS(T1_dataout_n[11]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L33 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[11]~155 at LC_X19_Y3_N3
--operation mode is arithmetic

T1L33_cout_0 = X1_result[11] & !X2_result[11] & !T1L30 # !X1_result[11] & (!T1L30 # !X2_result[11]);
T1L33 = CARRY(T1L33_cout_0);

--T1L34 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[11]~155COUT1_231 at LC_X19_Y3_N3
--operation mode is arithmetic

T1L34_cout_1 = X1_result[11] & !X2_result[11] & !T1L31 # !X1_result[11] & (!T1L31 # !X2_result[11]);
T1L34 = CARRY(T1L34_cout_1);


--NB10_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_9|add_sub_cella[4] at LC_X21_Y6_N8
--operation mode is arithmetic

NB10_add_sub_cella[4] = T1_dataout_n[10];

--NB10L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_9|add_sub_cella[4]~COUT at LC_X21_Y6_N8
--operation mode is arithmetic

NB10L5_cout_0 = T1_dataout_n[10];
NB10L5 = CARRY(NB10L5_cout_0);

--NB10L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_9|add_sub_cella[4]~COUTCOUT1_92 at LC_X21_Y6_N8
--operation mode is arithmetic

NB10L6_cout_1 = T1_dataout_n[10];
NB10L6 = CARRY(NB10L6_cout_1);


--NB1L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~86 at LC_X20_Y6_N2
--operation mode is normal

NB1L7 = !NB10L4 & (NB9L8 & (NB9_add_sub_cella[4]) # !NB9L8 & !T1_dataout_n[11]);


--NB10L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_9|add_sub_cella[5]~84 at LC_X21_Y6_N3
--operation mode is normal

NB10L7 = NB9L4 & (FB1L4) # !NB9L4 & NB9L7 & !FB1L4;


--FB1L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[67]~1025 at LC_X20_Y6_N6
--operation mode is normal

FB1L6 = NB1L7 & (NB10L7 & !NB10_add_sub_cella[4] # !NB10L7 & (T1_dataout_n[10])) # !NB1L7 & !NB10_add_sub_cella[4];


--FB1L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[60]~1026 at LC_X20_Y6_N8
--operation mode is normal

FB1L5 = NB9L8 & (!NB9_add_sub_cella[4]) # !NB9L8 & T1_dataout_n[11];


--NB1L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~87 at LC_X20_Y6_N9
--operation mode is normal

NB1L8 = NB10L4 & FB1L5 # !NB10L4 & !FB1L5 & NB10L7;


--NB1L9 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[5]~88 at LC_X20_Y6_N3
--operation mode is normal

NB1L9 = NB1L4 # NB1L8 # FB1L6;


--FB1L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[74]~1027 at LC_X20_Y6_N0
--operation mode is normal

FB1L7 = NB1L9 & (!NB1_add_sub_cella[4]) # !NB1L9 & T1_dataout_n[9];


--NB2L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[5]~84 at LC_X20_Y6_N7
--operation mode is normal

NB2L7 = NB1L4 & (FB1L6) # !NB1L4 & (NB1L8 & !FB1L6);


--NB2L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_11|add_sub_cella[5]~85 at LC_X20_Y6_N1
--operation mode is normal

NB2L8 = NB2L4 # NB2L7 # FB1L7;


--FB1L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[81]~1028 at LC_X19_Y6_N5
--operation mode is normal

FB1L8 = NB2L8 & (!NB2_add_sub_cella[4]) # !NB2L8 & T1_dataout_n[8];


--NB3L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[5]~84 at LC_X19_Y6_N7
--operation mode is normal

NB3L7 = NB2L4 & FB1L7 # !NB2L4 & !FB1L7 & NB2L7;


--NB3L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_12|add_sub_cella[5]~85 at LC_X19_Y6_N6
--operation mode is normal

NB3L8 = NB3L4 # NB3L7 # FB1L8;


--T1_dataout_n[7] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7] at LC_X19_Y4_N9
--operation mode is arithmetic

T1_dataout_n[7]_carry_eqn = (!T1L8 & T1L19) # (T1L8 & T1L20);
T1_dataout_n[7]_lut_out = X1_result[7] $ X2_result[7] $ T1_dataout_n[7]_carry_eqn;
T1_dataout_n[7] = DFFEAS(T1_dataout_n[7]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L22 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[7]~159 at LC_X19_Y4_N9
--operation mode is arithmetic

T1L22 = CARRY(X1_result[7] & !X2_result[7] & !T1L20 # !X1_result[7] & (!T1L20 # !X2_result[7]));


--NB4_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4] at LC_X18_Y5_N3
--operation mode is arithmetic

NB4_add_sub_cella[4] = T1_dataout_n[6];

--NB4L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]~COUT at LC_X18_Y5_N3
--operation mode is arithmetic

NB4L5_cout_0 = T1_dataout_n[6];
NB4L5 = CARRY(NB4L5_cout_0);

--NB4L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[4]~COUTCOUT1_94 at LC_X18_Y5_N3
--operation mode is arithmetic

NB4L6_cout_1 = T1_dataout_n[6];
NB4L6 = CARRY(NB4L6_cout_1);


--NB5L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~103 at LC_X18_Y6_N0
--operation mode is normal

NB5L7 = !NB4L4 & (NB3L8 & NB3_add_sub_cella[4] # !NB3L8 & (!T1_dataout_n[7]));


--NB4L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_13|add_sub_cella[5]~86 at LC_X19_Y6_N2
--operation mode is normal

NB4L7 = NB3L4 & (FB1L8) # !NB3L4 & NB3L7 & !FB1L8;


--FB1L10 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~1029 at LC_X18_Y6_N4
--operation mode is normal

FB1L10 = NB4L7 & (!NB4_add_sub_cella[4]) # !NB4L7 & (NB5L7 & T1_dataout_n[6] # !NB5L7 & (!NB4_add_sub_cella[4]));


--A1L75 is ddsout_rom~763 at LC_X18_Y6_N2
--operation mode is normal

A1L75 = !NB5L4 & !FB1L10 # !NB5_add_sub_cella[4];


--T1_dataout_n[5] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[5] at LC_X19_Y4_N7
--operation mode is arithmetic

T1_dataout_n[5]_carry_eqn = (!T1L8 & T1L3) # (T1L8 & T1L4);
T1_dataout_n[5]_lut_out = X1_result[5] $ X2_result[5] $ T1_dataout_n[5]_carry_eqn;
T1_dataout_n[5] = DFFEAS(T1_dataout_n[5]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L16 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[5]~163 at LC_X19_Y4_N7
--operation mode is arithmetic

T1L16_cout_0 = X1_result[5] & !X2_result[5] & !T1L3 # !X1_result[5] & (!T1L3 # !X2_result[5]);
T1L16 = CARRY(T1L16_cout_0);

--T1L17 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[5]~163COUT1_221 at LC_X19_Y4_N7
--operation mode is arithmetic

T1L17_cout_1 = X1_result[5] & !X2_result[5] & !T1L4 # !X1_result[5] & (!T1L4 # !X2_result[5]);
T1L17 = CARRY(T1L17_cout_1);


--FB1L9 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[88]~1030 at LC_X18_Y6_N7
--operation mode is normal

FB1L9 = NB3L8 & !NB3_add_sub_cella[4] # !NB3L8 & (T1_dataout_n[7]);


--A1L76 is ddsout_rom~764 at LC_X18_Y6_N5
--operation mode is normal

A1L76 = !NB5L4 & (!FB1L10);


--NB5L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_14|add_sub_cella[5]~104 at LC_X18_Y6_N6
--operation mode is normal

NB5L8 = NB4L4 & (FB1L9) # !NB4L4 & NB4L7 & !FB1L9 # !A1L76;


--A1L77 is ddsout_rom~765 at LC_X18_Y6_N3
--operation mode is normal

A1L77 = A1L67 & (NB5L8 & (A1L75) # !NB5L8 & T1_dataout_n[5]);


--T1_dataout_n[4] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[4] at LC_X19_Y4_N6
--operation mode is arithmetic

T1_dataout_n[4]_carry_eqn = (!T1L8 & T1L6) # (T1L8 & T1L7);
T1_dataout_n[4]_lut_out = X1_result[4] $ X2_result[4] $ !T1_dataout_n[4]_carry_eqn;
T1_dataout_n[4] = DFFEAS(T1_dataout_n[4]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L3 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[4]~167 at LC_X19_Y4_N6
--operation mode is arithmetic

T1L3_cout_0 = X1_result[4] & (X2_result[4] # !T1L6) # !X1_result[4] & X2_result[4] & !T1L6;
T1L3 = CARRY(T1L3_cout_0);

--T1L4 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[4]~167COUT1_219 at LC_X19_Y4_N6
--operation mode is arithmetic

T1L4_cout_1 = X1_result[4] & (X2_result[4] # !T1L7) # !X1_result[4] & X2_result[4] & !T1L7;
T1L4 = CARRY(T1L4_cout_1);


--J1_q_a[0] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[0] at M4K_X13_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
J1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);
J1_q_a[0]_PORT_A_address_reg = DFFE(J1_q_a[0]_PORT_A_address, J1_q_a[0]_clock_0, , , );
J1_q_a[0]_clock_0 = GLOBAL(PB1__clk0);
J1_q_a[0]_PORT_A_data_out = MEMORY(, , J1_q_a[0]_PORT_A_address_reg, , , , , , J1_q_a[0]_clock_0, , , , , );
J1_q_a[0] = J1_q_a[0]_PORT_A_data_out[0];

--J1_q_a[6] is ddsc:i_dds|lpm_rom:i_rom1|altrom:srom|altsyncram:rom_block|altsyncram_jqo:auto_generated|q_a[6] at M4K_X13_Y8
J1_q_a[0]_PORT_A_address = BUS(B1_acc[22], B1_acc[23], B1_acc[24], B1_acc[25], B1_acc[26], B1_acc[27], B1_acc[28], B1_acc[29], B1_acc[30], B1_acc[31]);