dds_sin.fit.eqn

用vhdl编写的程序

--T1_dataout_n[9] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[9] at LC_X19_Y3_N1
--operation mode is arithmetic

T1_dataout_n[9]_carry_eqn = (!T1L22 & T1L24) # (T1L22 & T1L25);
T1_dataout_n[9]_lut_out = X1_result[9] $ X2_result[9] $ T1_dataout_n[9]_carry_eqn;
T1_dataout_n[9] = DFFEAS(T1_dataout_n[9]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L27 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[9]~131 at LC_X19_Y3_N1
--operation mode is arithmetic

T1L27_cout_0 = X1_result[9] & !X2_result[9] & !T1L24 # !X1_result[9] & (!T1L24 # !X2_result[9]);
T1L27 = CARRY(T1L27_cout_0);

--T1L28 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[9]~131COUT1_227 at LC_X19_Y3_N1
--operation mode is arithmetic

T1L28_cout_1 = X1_result[9] & !X2_result[9] & !T1L25 # !X1_result[9] & (!T1L25 # !X2_result[9]);
T1L28 = CARRY(T1L28_cout_1);


--NB1_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[4] at LC_X19_Y6_N0
--operation mode is arithmetic

NB1_add_sub_cella[4] = T1_dataout_n[9];

--NB1L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[4]~COUT at LC_X19_Y6_N0
--operation mode is arithmetic

NB1L5_cout_0 = T1_dataout_n[9];
NB1L5 = CARRY(NB1L5_cout_0);

--NB1L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_10|add_sub_cella[4]~COUTCOUT1_96 at LC_X19_Y6_N0
--operation mode is arithmetic

NB1L6_cout_1 = T1_dataout_n[9];
NB1L6 = CARRY(NB1L6_cout_1);


--T1_dataout_n[10] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[10] at LC_X19_Y3_N2
--operation mode is arithmetic

T1_dataout_n[10]_carry_eqn = (!T1L22 & T1L27) # (T1L22 & T1L28);
T1_dataout_n[10]_lut_out = X1_result[10] $ X2_result[10] $ !T1_dataout_n[10]_carry_eqn;
T1_dataout_n[10] = DFFEAS(T1_dataout_n[10]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L30 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[10]~135 at LC_X19_Y3_N2
--operation mode is arithmetic

T1L30_cout_0 = X1_result[10] & (X2_result[10] # !T1L27) # !X1_result[10] & X2_result[10] & !T1L27;
T1L30 = CARRY(T1L30_cout_0);

--T1L31 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[10]~135COUT1_229 at LC_X19_Y3_N2
--operation mode is arithmetic

T1L31_cout_1 = X1_result[10] & (X2_result[10] # !T1L28) # !X1_result[10] & X2_result[10] & !T1L28;
T1L31 = CARRY(T1L31_cout_1);


--NB9_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[4] at LC_X21_Y6_N1
--operation mode is arithmetic

NB9_add_sub_cella[4] = T1_dataout_n[11];

--NB9L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[4]~COUT at LC_X21_Y6_N1
--operation mode is arithmetic

NB9L5_cout_0 = T1_dataout_n[11];
NB9L5 = CARRY(NB9L5_cout_0);

--NB9L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[4]~COUTCOUT1_194 at LC_X21_Y6_N1
--operation mode is arithmetic

NB9L6_cout_1 = T1_dataout_n[11];
NB9L6 = CARRY(NB9L6_cout_1);


--T1_dataout_n[12] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[12] at LC_X19_Y3_N4
--operation mode is arithmetic

T1_dataout_n[12]_carry_eqn = (!T1L22 & T1L33) # (T1L22 & T1L34);
T1_dataout_n[12]_lut_out = X1_result[12] $ X2_result[12] $ !T1_dataout_n[12]_carry_eqn;
T1_dataout_n[12] = DFFEAS(T1_dataout_n[12]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L36 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[12]~139 at LC_X19_Y3_N4
--operation mode is arithmetic

T1L36 = CARRY(X1_result[12] & (X2_result[12] # !T1L34) # !X1_result[12] & X2_result[12] & !T1L34);


--NB8_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[4] at LC_X21_Y3_N1
--operation mode is arithmetic

NB8_add_sub_cella[4] = T1_dataout_n[12];

--NB8L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[4]~COUT at LC_X21_Y3_N1
--operation mode is arithmetic

NB8L5_cout_0 = T1_dataout_n[12];
NB8L5 = CARRY(NB8L5_cout_0);

--NB8L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[4]~COUTCOUT1_150 at LC_X21_Y3_N1
--operation mode is arithmetic

NB8L6_cout_1 = T1_dataout_n[12];
NB8L6 = CARRY(NB8L6_cout_1);


--T1_dataout_n[13] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[13] at LC_X19_Y3_N5
--operation mode is arithmetic

T1_dataout_n[13]_carry_eqn = T1L36;
T1_dataout_n[13]_lut_out = X2_result[13] $ X1_result[13] $ T1_dataout_n[13]_carry_eqn;
T1_dataout_n[13] = DFFEAS(T1_dataout_n[13]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L38 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[13]~143 at LC_X19_Y3_N5
--operation mode is arithmetic

T1L38_cout_0 = X2_result[13] & !X1_result[13] & !T1L36 # !X2_result[13] & (!T1L36 # !X1_result[13]);
T1L38 = CARRY(T1L38_cout_0);

--T1L39 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[13]~143COUT1_233 at LC_X19_Y3_N5
--operation mode is arithmetic

T1L39_cout_1 = X2_result[13] & !X1_result[13] & !T1L36 # !X2_result[13] & (!T1L36 # !X1_result[13]);
T1L39 = CARRY(T1L39_cout_1);


--NB7_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_6|add_sub_cella[4] at LC_X20_Y3_N0
--operation mode is arithmetic

NB7_add_sub_cella[4] = T1_dataout_n[13];

--NB7L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_6|add_sub_cella[4]~COUT at LC_X20_Y3_N0
--operation mode is arithmetic

NB7L5_cout_0 = T1_dataout_n[13];
NB7L5 = CARRY(NB7L5_cout_0);

--NB7L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_6|add_sub_cella[4]~COUTCOUT1_86 at LC_X20_Y3_N0
--operation mode is arithmetic

NB7L6_cout_1 = T1_dataout_n[13];
NB7L6 = CARRY(NB7L6_cout_1);


--T1_dataout_n[14] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14] at LC_X19_Y3_N6
--operation mode is arithmetic

T1_dataout_n[14]_carry_eqn = (!T1L36 & T1L38) # (T1L36 & T1L39);
T1_dataout_n[14]_lut_out = X1_result[14] $ !T1_dataout_n[14]_carry_eqn;
T1_dataout_n[14] = DFFEAS(T1_dataout_n[14]_lut_out, GLOBAL(sysclk), VCC, , , , , , );

--T1L41 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14]~147 at LC_X19_Y3_N6
--operation mode is arithmetic

T1L41_cout_0 = X1_result[14] & !T1L38;
T1L41 = CARRY(T1L41_cout_0);

--T1L42 is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[14]~147COUT1_235 at LC_X19_Y3_N6
--operation mode is arithmetic

T1L42_cout_1 = X1_result[14] & !T1L39;
T1L42 = CARRY(T1L42_cout_1);


--MB1_add_sub_cella[4] is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4] at LC_X19_Y3_N8
--operation mode is arithmetic

MB1_add_sub_cella[4] = T1_dataout_n[14];

--MB1L5 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~COUT at LC_X19_Y3_N8
--operation mode is arithmetic

MB1L5_cout_0 = T1_dataout_n[14];
MB1L5 = CARRY(MB1L5_cout_0);

--MB1L6 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[4]~COUTCOUT1_79 at LC_X19_Y3_N8
--operation mode is arithmetic

MB1L6_cout_1 = T1_dataout_n[14];
MB1L6 = CARRY(MB1L6_cout_1);


--T1_dataout_n[15] is mul_6:mul|kk:u1|altmult_add:ALTMULT_ADD_component|mult_add_rh23:auto_generated|alt_mac_out:mac_out4|dataout_n[15] at LC_X19_Y3_N7
--operation mode is normal

T1_dataout_n[15]_carry_eqn = (!T1L36 & T1L41) # (T1L36 & T1L42);
T1_dataout_n[15]_lut_out = T1_dataout_n[15]_carry_eqn;
T1_dataout_n[15] = DFFEAS(T1_dataout_n[15]_lut_out, GLOBAL(sysclk), VCC, , , , , , );


--LB1_cout is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_oe8:add_sub_4|cout at LC_X20_Y3_N8
--operation mode is arithmetic

LB1_cout_cout_0 = T1_dataout_n[15];
LB1_cout = CARRY(LB1_cout_cout_0);

--LB1L4 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_oe8:add_sub_4|cout~COUT1_1 at LC_X20_Y3_N8
--operation mode is arithmetic

LB1L4_cout_1 = T1_dataout_n[15];
LB1L4 = CARRY(LB1L4_cout_1);


--MB1L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_pe8:add_sub_5|add_sub_cella[5]~71 at LC_X20_Y3_N9
--operation mode is normal

MB1L7 = !LB1_cout & T1_dataout_n[15];


--FB1L1 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[39]~1021 at LC_X20_Y3_N4
--operation mode is normal

FB1L1 = MB1L7 & !MB1_add_sub_cella[4] # !MB1L7 & (MB1L4 & !MB1_add_sub_cella[4] # !MB1L4 & (T1_dataout_n[14]));


--FB1L2 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1022 at LC_X20_Y3_N5
--operation mode is normal

FB1L2 = NB7L4 # FB1L1 # MB1L7 & MB1L4;


--FB1L3 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[46]~1023 at LC_X20_Y3_N6
--operation mode is normal

FB1L3 = FB1L2 & (!NB7_add_sub_cella[4]) # !FB1L2 & T1_dataout_n[13];


--NB8L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[5]~141 at LC_X20_Y3_N2
--operation mode is normal

NB8L7 = FB1L1 & (NB7L4) # !FB1L1 & MB1L7 & MB1L4 & !NB7L4;


--NB8L8 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_7|add_sub_cella[5]~142 at LC_X20_Y3_N3
--operation mode is normal

NB8L8 = NB8L4 # NB8L7 # FB1L3;


--FB1L4 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[53]~1024 at LC_X20_Y6_N4
--operation mode is normal

FB1L4 = NB8L8 & (!NB8_add_sub_cella[4]) # !NB8L8 & T1_dataout_n[12];


--NB9L7 is mul_6:mul|ll:u2|lpm_divide:lpm_divide_component|lpm_divide_k5j:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_qe8:add_sub_8|add_sub_cella[5]~185 at LC_X20_Y3_N7
--operation mode is normal