mulx.vhd

数字秒表的整个设计以及程序．波形仿真都在里面的了

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY  mulx IS
PORT(
		clk	                : IN	STD_LOGIC;
		msh, msl,sl,ml		: IN	STD_LOGIC_VECTOR( 3 downto 0);
        sh,mh	            : IN	STD_LOGIC_VECTOR( 2 downto 0);
        q                   : buffer std_logic_vector(2 downto 0);
        out1                : OUT	STD_LOGIC_VECTOR( 3 downto 0);
        seg                 : OUT	STD_LOGIC_VECTOR( 5 downto 0)
   );
END mulx;


ARCHITECTURE one OF mulx IS
BEGIN
process(clk)
begin
   if clk'event and clk='1' then
        if q<5  then q<=q+1;
         else q<="000";
        end if;
   end if;
end process;

process(q)
begin
    case q is
        when "000"=>out1<=msl;seg<="111110";
        when "001"=>out1<=msh;seg<="111101";
        when "010"=>out1<=sl;seg<="111011";
        when "011"=>out1<='0'&sh;seg<="110111";
        when "100"=>out1<=ml;seg<="111111";
        when "101"=>out1<='0'&mh;seg<="011111";
        when others=>null;
    end case;
end process;
END one;