drv_glcd.c

UCOS在LPC2378开发板里面的原版移植程序.并且里面还包含了最新的UCPROBE,很强哦,另外还有UCOSVIEW和大量文档.

/*************************************************************************
 *
 *    Used with ICCARM and AARM.
 *
 *    (c) Copyright IAR Systems 2006
 *
 *    File name   : drv_glcd.c
 *    Description : Graphic LCD driver
 *
 *    History :
 *    1. Date        : December 2, 2006
 *       Author      : Stanimir Bonev
 *       Description : Create
 *
 *    $Revision: 1.0 $
 **************************************************************************/

#include "drv_glcd.h"
#include <assert.h>
#include <includes.h>
                                                                /* delay definition */
#define GLCD_DLY_10US                        80                 // 10us
#define GLCD_RESET_DLY                       50                 // 5ms
#define GLCD_BOOSTER_ON_DLY                1200                 // 120 ms

/*************************************************************************
 * Function Name: Dly100us
 * Parameters: void *arg
 * Return: void
 *
 * Description: Delay [100us]
 *		
 *************************************************************************/
void  Dly100us (void *arg)
{
    volatile  Int32U  Dly;
    volatile  Int32U  Dly100;


    for(Dly = (Int32U)arg; Dly; Dly--) {
        for(Dly100 = 500; Dly100; Dly100--) {
            ;
        }
    }
}


/*************************************************************************
 * Function Name: SYS_GetFsclk
 * Parameters: none
 * Return: Int32U
 *
 * Description: return Sclk [Hz]
 *
 *************************************************************************/
Int32U SYS_GetFsclk(void)
{
Int32U Mul = 1, Div = 1, Osc, Fsclk;
  if(PLLSTAT_bit.PLLC)
  {
    // when PLL is connected
    Mul = PLLSTAT_bit.MSEL + 1;
    Div = PLLSTAT_bit.NSEL + 1;
  }

  // Find clk source
  switch(CLKSRCSEL_bit.CLKSRC)
  {
  case 0:
    Osc = I_RC_OSC_FREQ;
    break;
  case 1:
    Osc = MAIN_OSC_FREQ;
    break;
  case 2:
    Osc = RTC_OSC_FREQ;
    break;
  default:
    Osc = 0;
  }
  // Calculate system frequency
  Fsclk = Osc*Mul*2;
  Fsclk /= Div*(CCLKCFG+1);
  return(Fsclk);
}
/*************************************************************************
 * Function Name: SYS_GetFpclk
 * Parameters: Int32U Periphery
 * Return: Int32U
 *
 * Description: return Pclk [Hz]
 *
 *************************************************************************/
Int32U SYS_GetFpclk(Int32U Periphery)
{
Int32U Fpclk;
pInt32U pReg = (pInt32U)((Periphery < 32)?&PCLKSEL0:&PCLKSEL1);

  Periphery  &= 0x1F;   // %32
  Fpclk = SYS_GetFsclk();
  // find peripheral appropriate periphery divider
  switch((*pReg >> Periphery) & 3)
  {
  case 0:
    Fpclk /= 4;
    break;
  case 1:
    break;
  case 2:
    Fpclk /= 2;
    break;
  default:
    Fpclk /= 8;
  }
  return(Fpclk);
}
static const GLCD_CmdCtrl_t GLCD_Cmd_Iss0[GLCD_CMD_NUMB] = {

                                        // (ISS 0 1)
    {0x00, GLCD_WRITE, 0, 0},           // NOP              - No Operation
    {0x10, GLCD_WRITE, 0, 0},           // SLPIN            - Sleep in & booster off
    {0x11, GLCD_WRITE, 0, 0},           // SLPOUT           - Sleep out & booster on
    {0x13, GLCD_WRITE, 0, 0},           // PTLOUT (NORON)   - Partial off (Normal)
    {0x20, GLCD_WRITE, 0, 0},           // INVOFF           - Display inversion off (normal)
    {0x21, GLCD_WRITE, 0, 0},           // INVON            - Display inversion on
    {0x28, GLCD_WRITE, 0, 0},           // DISPOFF          - Display off
    {0x29, GLCD_WRITE, 0, 0},           // DISPON           - Display on

    {0x2A, GLCD_WRITE, 0, 2},           // CASET            - Column address set
                                        // X_ADR start: 0h <= XS <= 83h
                                        // X_ADR end:   0h <= XS <= 83h

    {0x2B, GLCD_WRITE, 0, 2},           // RASET            - Row address set
                                        // Y_ADR start: 0h <= YS <= 83h
                                        // Y_ADR end:   0h <= YS <= 83h

    {0x2C, GLCD_WRITE, 0, (Int32U)-1},  // RAMWR            - Memory write
    {0x2D, GLCD_WRITE, 0, 20},          // RGBSET           - Color set for 256 color display

    {0x37, GLCD_WRITE, 0, 1},           // VSCSAD           - Scroll start address of RAM
                                        // SSA = 0, 1, 2,