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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> MIPS R3000, R4000, R4650 </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-mips.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-mips3.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-ppc.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="84661">E.4 Architecture Considerations</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84662"> </a>This section describes the following characteristics of the MIPS architecture that you should keep in mind as you write a VxWorks application:</p></dl><dl class="margin"><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84663"> </a>Gprel addressing </li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84664"> </a>Reserved registers </li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84665"> </a>Floating-point support </li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84666"> </a>Interrupts </li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84667"> </a>Virtual memory mapping </li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84668"> </a>64-bit support </li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84669"> </a>Memory layout </li></ul></p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84672">Gprel Addressing</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84675"> </a>The VxWorks kernel uses <i class="term">gprel</i> (<b class="symbol_lc">gp</b>-relative) addressing. However, the VxWorks module loader cannot dynamically load tasks that use gprel addressing.</p><dd><p class="Body"><a name="84677"> </a>To keep the loader from returning an error, compile application tasks with the <b class="command">-G 0</b> option. This option tells the compiler not to use the global pointer.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84679">Reserved Registers</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84680"> </a>Registers <b class="symbol_lc">k0</b> and <b class="symbol_lc">k1</b> are reserved for VxWorks kernel use, following standard MIPS usage. The <b class="symbol_lc">gp</b> register is also reserved for the VxWorks kernel, because only the kernel uses gprel addressing, as discussed in above. Avoid using these registers in your applications.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84684">Floating-Point Support</a></i></h4></font><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84685">R4650</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84686"> </a>For the R4650, single precision hardware floating-point support is included by <b class="symbol_UC">INCLUDE_HW_FP </b>(which is included by default in the project facility VxWorks view). Double precision floating-point support is provided by software emulation when you use <b class="symbol_lc">-msoft-float</b>. (Note that <b class="symbol_UC">INCLUDE_SW_FP</b> is not required with <b class="symbol_lc">-msoft-float</b> for the R4650.)</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84687">R3000 and R4000</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84688"> </a>If your MIPS board includes a floating-point coprocessor (CP1), we recommend you use it for best performance. </p><dd><p class="Body"><a name="84690"> </a>However, if this chip is not available, you can use the GNU<b class="command"> </b>compiler <b class="command">-msoft-float</b> option. This option keeps all floating-point values in integer registers (a pair of them for double-precision) and emulates all floating-point arithmetic.</p><dd><p class="Body"><a name="84691"> </a>To use this software emulation support, select <b class="symbol_UC">INCLUDE_SW_FP</b> in the project facility VxWorks view and unselect <b class="symbol_UC">INCLUDE_HW_FP</b>. Then, in the BSP directory, build VxWorks with the following command:</p><dl class="margin"><dd><pre class="Code2"><b><a name="84692"></b><tt class="output">%</tt><b> make [CPU=<i class="textVariable">cpuType</i>] TOOL=sfgnu</a></b></pre></dl></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84694">Interrupts</a></i></h4></font><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84696">MIPS Interrupts </a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84697"> </a>The MIPS architecture has inputs for six external hardware interrupts and two software interrupts. In cases where the number of hardware interrupts is insufficient, board manufacturers can multiplex several interrupts on one or more interrupt lines. </p><dd><p class="Body"><a name="84698"> </a>The MIPS CPU treats exceptions and interrupts in the same way: it branches to a common vector and provides status and cause registers that let system software determine the CPU state. The MIPS CPU does not switch to an interrupt stack or exception stack, nor does it generate an IACK cycle. These functions must be implemented in software or board-level hardware (for example, the VMEbus IACK cycle is a board-level hardware function). VxWorks for MIPS has implemented a single interrupt stack, and uses task stacks for exception conditions. </p><dd><p class="Body"><a name="84702"> </a>Because the MIPS CPU does not provide an IACK cycle, your interrupt handler must acknowledge (or clear) the interrupt condition. If the interrupt handler does not acknowledge the interrupt, VxWorks hangs while trying to process the interrupt condition.</p><dd><p class="Body"><a name="84703"> </a>VxWorks for MIPS uses a 256-entry table of vectors. You can attach exception or interrupt handlers to any given vector with the routines <b class="routine"><i class="routine">intConnect</i></b><b>(</b> <b>)</b> and <b class="routine"><i class="routine">intVecSet</i></b><b>(</b> <b>)</b>. The files <i class="textVariable">installDir</i><b class="file">/target/h/arch/mips/ivMips.h</b> and<b class="file"> </b><i class="textVariable">bspname</i><b class="file">.h</b> list the vectors used by VxWorks.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84709">Interrupt Support Routines</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84711"> </a>Because the MIPS architecture does not use interrupt levels, the <b class="routine"><i class="routine">intLevelSet</i></b><b>(</b> <b>)</b> routine is not implemented. The six external interrupts and two software interrupts can be masked or enabled by manipulating eight bits in the status register with <b class="routine"><i class="routine">intDisable</i></b><b>(</b> <b>)</b> and <b class="routine"><i class="routine">intEnable</i></b><b>(</b> <b>)</b>. Be careful to pass correct arguments to these routines, because the MIPS status register controls much more than just interrupt generation. </p><dd><p class="Body"><a name="84716"> </a>For interrupt control, the routines <b class="routine"><i class="routine">intLock</i></b><b>(</b> <b>)</b> and <b class="routine"><i class="routine">intUnlock</i></b><b>(</b> <b>)</b> are recommended. All interrupts are blocked when calling <b class="routine"><i class="routine">intLock</i></b><b>(</b> <b>)</b>. The routine <b class="routine"><i class="routine">intVecBaseSet</i></b><b>(</b> <b>)</b> has no meaning on the MIPS; calling it has no effect. </p><dd><p class="Body"><a name="84718"> </a>To change the default status register with which all tasks are spawned, use the routine <b class="routine"><i class="routine">taskSRInit</i></b><b>(</b> <b>)</b>. If used, call this routine before <b class="routine"><i class="routine">kernelInit</i></b><b>(</b> <b>)</b> in <b class="routine"><i class="routine">sysHwInit</i></b><b>(</b> <b>)</b>. <b class="routine"><i class="routine">taskSRInit</i></b><b>(</b> <b>)</b> is provided in case your BSP must mask interrupts from all tasks. For example, the FPA interrupt must be disabled for all tasks.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84721">VMEbus Interrupt Handling</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84722"> </a>The processing of VMEbus interrupts is the only case where it is not necessary for an interrupt handler to acknowledge the interrupt condition. If you define the option <b class="symbol_UC">VME_VECTORED </b>as TRUE in<b class="file"> config.h</b> (and rebuild VxWorks), <i class="emphasis">all</i> VMEbus interrupts are acknowledged by the low-level exception/interrupt handling code. The VxWorks interrupt vector number corresponds to the VMEbus interrupt vector returned by the VMEbus IACK cycle. With this interrupt handling scheme, VxWorks for MIPS allows multiple VMEbus boards to share the same VMEbus interrupt level without requiring further decoding by a user-attached interrupt handler. </p><dd><p class="Body"><a name="84725"> </a>You can still bind to VMEbus interrupts without vectored interrupts enabled, as long as the VMEbus interrupt condition is acknowledged with <b class="routine"><i class="routine">sysBusIntAck</i></b><b>(</b> <b>)</b> (as defined in <b class="file">sysLib.c</b>). In this case, there is no longer a direct correlation with the vector number returned during the VMEbus IACK cycle. The vector number used to attach the interrupt handler corresponds to one of the seven VMEbus interrupt levels as defined in <i class="textVariable">bspname</i><b class="file">.h.</b> The mapping of the seven VMEbus interrupts to a single MIPS interrupt is board-dependent. </p><dd><p class="Body"><a name="84727"> </a>Vectored interrupts do not change the handling of any interrupt condition except VMEbus interrupts. All the necessary interrupt-acknowledge routines are provided in either <b class="file">sysLib.c</b> or <b class="file">sysALib.s</b>.</p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="84902"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>Not all boards support VME-vectored interrupts. For more information, see the BSP reference entries.<b> </b></div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84740">Virtual Memory Mapping</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84741"> </a>VxWorks for MIPS operates exclusively in kernel mode and makes use of the <b class="keyword">kseg0</b> and <b class="keyword">kseg1</b> address spaces. A physical addressing range of 512 MB is available. Use of the on-chip <i class="term">translation lookaside buffer</i> (TLB) is not supported.</p><b class="BulletHead-run"><li type="disc"><a name="84742"> </a><font face="Helvetica, sans-serif" size="-1" class="sans">kseg0 . </font></b><dl class="margin"><dd><div class="Indent"><a name="84743"> </a>When the most significant three bits of the virtual address are 100, the 2<sup>29</sup>-byte (512 MB) kernel physical space labeled <b class="keyword">kseg0</b> is the virtual address space selected. References to <b class="keyword">kseg0</b> are not mapped through the TLB; the physical address selected is defined by subtracting 0x8000 0000 from the virtual address. Caches are always enabled for accesses to these addresses.</div><br></dl>⌨️ 快捷键说明
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