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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> Motorola MC680x0 </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-680x0.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-680x03.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-sparc.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="84594">A.4 Architecture Considerations</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84595"> </a>This section describes the following characteristics of the MC680<i class="textVariable">x</i>0 processors (particularly the MC68040 and MC68060) that you should keep in mind as you write a VxWorks application:</p></dl><dl class="margin"><ul class="BulletSingle" type="disc"><li><a name="84596"> </a>MC68060 unimplemented integer instructions </li></ul><ul class="BulletSingle" type="disc"><li><a name="84597"> </a>Double-word integers </li></ul><ul class="BulletSingle" type="disc"><li><a name="84598"> </a>Interrupt stack </li></ul><ul class="BulletSingle" type="disc"><li><a name="84599"> </a>MC68060 superscalar pipeline </li></ul><ul class="BulletSingle" type="disc"><li><a name="84600"> </a>Caches </li></ul><ul class="BulletSingle" type="disc"><li><a name="84601"> </a>Memory Management Unit </li></ul><ul class="BulletSingle" type="disc"><li><a name="84602"> </a>Floating-point support </li></ul><ul class="BulletSingle" type="disc"><li><a name="84603"> </a>Memory layout </li></ul></dl><dl class="margin"><dd><p class="Body"><a name="84604"> </a>Note that discussion of the MC68040 also applies to the MC68LC040 unless otherwise noted. The MC68LC040 is a derivative of the MC68040 and differs only in that it has no floating-point unit.</p><dd><p class="Body"><a name="84605"> </a>For comprehensive documentation of Motorola architectures, see the appropriate Motorola microprocessor user's manual.</p><dd><p class="Body"><a name="84606"> </a>The names of macros specific to these architectures, and specialized terms in the remainder of this section, match the terms used by the Motorola manuals.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84607">MC68060 Unimplemented Integer Instructions</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84609"> </a>Neither the 64-bit divide and multiply instructions, nor the <b class="symbol_lc">movep</b>, <b class="symbol_lc">cmp2</b>, <b class="symbol_lc">chk2</b>, <b class="symbol_lc">cas</b>, and <b class="symbol_lc">cas2</b> instructions are implemented on the MC68060 processor. To eliminate these restrictions, VxWorks integrates the software emulation provided in the Motorola MC68060 software package, version B1. This package contains an exception handler that allows full emulation of the instructions listed above. VxWorks connects this exception handler to the unimplemented-integer-instruction exception (vector 61).</p><dd><p class="Body"><a name="84610"> </a>The Motorola exception handler allows the host operating system to add or to substitute its own routines. VxWorks does not add or substitute any routines; the instruction emulation is the full Motorola implementation.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84611">Double-word Integers: <b class="symbol_lc">long long</b></a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84613"> </a><b class="symbol_lc"></b>The double-word integer <b class="symbol_lc">long long</b> is not supported, except as an artifact of your particular architecture and compiler. For more information about handling unsupported features, please see the <i class="title">Customer Support User's Guide</i>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84614">Interrupt Stack</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84616"> </a><b></b>VxWorks uses a separate interrupt stack whenever the underlying architecture supports it. All MC680<i class="textVariable">x</i>0 processors, except the MC68060, have an interrupt stack.</p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84618">The MC680x0 Interrupt Stack</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84619"> </a>For all MC680<i class="textVariable">x</i>0 processors that have an interrupt stack, VxWorks uses the separate interrupt stack instead of the current task stack when the processor takes an interrupt.</p><dd><p class="Body"><a name="84621"> </a>The interrupt stack size is defined by the <b class="symbol_UC">ISR_STACK_SIZE</b> parameter in the project facility under <b class="symbol_UC">INCLUDE_KERNEL</b>. The default size of the interrupt stack is 1000 bytes.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84624">MC68060: No Interrupt Stack</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="86048"> </a>When the MC68060 processor takes an interrupt, VxWorks uses the current supervisor stack. To avoid stack overflow, spawn every task with a stack big enough to hold both the task stack and the interrupt stack.</p><dd><p class="Body"><a name="86050"> </a>The routine <b class="routine"><i class="routine">checkStack</i></b><b>( )</b>, which is built into the Tornado shell, displays the stack state for each task and also for the interrupt stack. Because this routine is the same for all processors that VxWorks supports, <b class="routine"><i class="routine">checkStack</i></b><b>( )</b> displays a line for the interrupt stack state. For the MC68060, the values appearing on this line are meaningless.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84630">MC68060 Superscalar Pipeline</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84631"> </a>The MC68060 implements a superscalar pipeline that allows multiple instructions to be executed in a single machine cycle. This feature can be enabled or disabled by setting or clearing the ESS (Enable SuperScalar) bit of the Processor Configuration Register (PCR). For this architecture, VxWorks provides two routines to enable and disable the superscalar pipeline, declared as follows:</p></dl><dl class="margin"><dd><pre class="Code"><b><a name="84633"> void vxSSEnable (void) void vxSSDisable (void)</a></b></pre></dl><dl class="margin"><dd><p class="Body"><a name="84634"> </a>In the default configuration, VxWorks enables the superscalar pipeline.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84636">Caches</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84637"> </a>The MC68000 and MC68010 processors do not have caches. The MC68020 has only a 256-byte instruction cache; see the general cache information presented in <a href="c-iosys9.html#85815"><i class="title">Cache Coherency</i></a>.</p><dd><p class="Body"><a name="84641"> </a>The MC68040 has 4KB instruction and data caches, and the MC68060 has 8KB instruction and data caches. The following subsections augment the information in <a href="c-iosys9.html#85815"><i class="title">Cache Coherency</i></a>.</p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84647">MC68040 Caches</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84648"> </a>The MC68040 processor contains an instruction cache and a data cache. By default, VxWorks uses both caches; that is, both are enabled. To disable the instruction cache, highlight the <b class="symbol_UC">USER_I_CACHE_ENABLE</b> macro in the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab under <b class="symbol_UC">INCLUDE_CACHE_ENABLE</b> and remove the <b class="symbol_UC">TRUE</b>; to disable the data cache, highlight the <b class="symbol_UC">USER_D_CACHE_ENABLE </b>macro and remove the <b class="symbol_UC">TRUE</b>.</p><dd><p class="Body"><a name="84651"> </a>These caches can be set to the following modes: </p></dl><dl class="margin"><ul class="DashSingle" type="circle"><li><a name="84652"> </a>cacheable writethrough (the default for both caches) </li></ul><ul class="DashSingle" type="circle"><li><a name="84653"> </a>cacheable copyback </li></ul><ul class="DashSingle" type="circle"><li><a name="84654"> </a>cache-inhibited serialized </li></ul><ul class="DashSingle" type="circle"><li><a name="84655"> </a>cache-inhibited not-serialized </li></ul></dl><dl class="margin"><dd><p class="Body"><a name="84657"> </a>Choose the mode by setting the <b class="symbol_UC">USER_I_CACHE_MODE</b> parameter or the <b class="symbol_UC">USER_D_CACHE_MODE</b> parameter in the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab under <b class="symbol_UC">INCLUDE_CACHE_MODE</b>. The list of possible values for these macros is defined in <i class="textVariable">installDir</i><b class="file">/target/h/cacheLib.h</b>. </p><dd><p class="Body"><a name="84659"> </a>For most boards, the cache capabilities must be used with the MMU to resolve cache coherency problems. In that situation, the page descriptor for each page selects the cache mode. This page descriptor is configured by filling the <b class="keyword">sysPhysMemDesc[] </b>data structure defined in the BSP <i class="textVariable">installDir</i><b class="file">/target/config/</b><i class="textVariable">bspname</i><b class="file">/sysLib.c</b> file. (For more information about cache coherency, see the <b class="library">cacheLib</b> reference entry. See also <a href="c-vm.html#84369"><i class="title">7. Virtual Memory Interface</i></a> for information on VxWorks MMU support. For MMU information specific to the MC680<i class="textVariable">x0</i> family, see <a href="x-680x04.html#84719"><i class="title">Memory Management Unit</i></a>.)</p><dd><p class="Body"><a name="84668"> </a>The MC68040 caches do not support cache locking and unlocking. Thus the <b class="routine"><i class="routine">cacheLock</i></b><b>( )</b> and <b class="routine"><i class="routine">cacheUnlock</i></b><b>( )</b> routines have no effect on this target, and always return <b class="symbol_UC">ERROR</b>.</p><dd><p class="Body"><a name="84673"> </a>The <b class="routine"><i class="routine">cacheClear</i></b><b>( )</b> and <b class="routine"><i class="routine">cacheInvalidate</i></b><b>( )</b> routines are very similar. Their effect depends on the cache:</p></dl><dl class="margin"><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84677"> </a>With the data cache, <b class="routine"><i class="routine">cacheClear</i></b><b>( )</b> first pushes dirty data<sup><a href="#foot"><b class="FootnoteMarker">1</b></a></sup> to memory (if the cache line contains any) and then invalidates the cache line, while <b class="routine"><i class="routine">cacheInvalidate</i></b><b>( )</b> just invalidates the line (in which case any dirty data contained in this line is lost).</li></ul></p><p class="listspace"><ul class="Bullet" type="disc"><li><a name="84678"> </a>For the instruction cache, both routines have the same result: they invalidate the cache lines.</li></ul></p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84682">MC68060 Caches</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84683"> </a>VxWorks for the MC68060 processor provides all the cache features of the MC68040, and some additional features.</p></dl><dl class="margin"><b class="HU-bullet"><li><a name="84685"> </a><font face="Helvetica, sans-serif" size="-1" class="sans">Instruction and Data Cache</font></li></b></dl><dl class="margin"><dd><p class="Body"><a name="85770"> </a>Motorola has introduced a change of terminology with the MC68060: the mode called "cache-inhibited serialized mode" on the MC68040 is called "cache-inhibited precise mode" on the MC68060, and the MC68040's "cache-inhibited not-serialized mode" is replaced by "cache-inhibited imprecise mode" on the MC68060. </p><dd><p class="Body"><a name="85775"> </a>To make your code consistent with this change, you can use the macros<sup><a href="#foot"><b class="FootnoteMarker">2</b></a></sup> <b class="symbol_UC">CACHE_INH_PRECISE</b> and <b class="symbol_UC">CACHE_INH_IMPRECISE</b> with VxWorks cache routines when writing specifically for the MC68060, instead of using the MC68040-oriented macro names <b class="symbol_UC">CACHE_INH_SERIAL</b> and <b class="symbol_UC">CACHE_INH_NONSERIAL</b>. (The corresponding macros in each pair have the same definition, however, to make MC68040 object code compatible with the MC68060.)</p><dd><p class="Body"><a name="84695"> </a>A four-entry first-in-first-out (FIFO) buffer is implemented on the MC68060. This buffer, used by the cacheable writethrough and cache inhibited imprecise mode, is enabled by default. Two VxWorks routines are available to enable or disable this store buffer. Their names and prototypes are declared as follows:</p><dl class="margin"><dd><pre class="Code2"><b><a name="84698">void cacheStoreBufEnable (void) void cacheStoreBufDisable (void)</a></b></pre></dl><dd><p class="Body"><a name="84700"> </a>On the MC68060, the instruction cache and data cache can be locked by software. Thus, on this architecture (unlike for the MC68040), the <b class="routine"><i class="routine">cacheLock</i></b><b>( )</b> and <b class="routine"><i class="routine">cacheUnlock</i></b><b>( )</b> routines are effective.</p><dd><p class="Body"><a name="84703"> </a>VxWorks does not support the MC68060 option to use only half of the instruction cache or data cache.</p></dl><dl class="margin"><b class="HU-bullet"><li><a name="84705"> </a><font face="Helvetica, sans-serif" size="-1" class="sans">Branch Cache </font></li></b></dl><dl class="margin"><dd><p class="Body"><a name="84706"> </a>In addition to the instruction cache and the data cache, the MC68060 contains a branch cache that VxWorks supports as an additional cache. Use the name <b class="symbol_UC">BRANCH_CACHE</b> to refer to this cache with the VxWorks cache routines.</p><dd><p class="Body"><a name="84708"> </a>Most routines available for both instruction and data caches are also available for the branch cache. However, the branch cache cannot be locked; thus, the <b class="routine"><i class="routine">cacheLock</i></b><b>( )</b> and <b class="routine"><i class="routine">cacheUnlock</i></b><b>( )</b> routines have no effect and always return <b class="symbol_UC">ERROR</b>.</p><dd><p class="Body"><a name="84712"> </a>The branch cache uses only one operating mode and does not require a macro to specify the current mode. In the default configuration, VxWorks enables the branch cache. This option can be removed by highlighting the <b class="symbol_UC">USER_B_CACHE_ENABLE</b> macro in the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab under <b class="symbol_UC">INCLUDE_CACHE_ENABLE</b> and remove the <b class="symbol_UC">TRUE</b>.</p><dd><p class="Body"><a name="84714"> </a>The branch cache can be invalidated only in its entirety. Trying to invalidate one branch cache line, or, as for the instruction cache, clearing the branch cache, invalidates the whole cache.</p><dd><p class="Body"><a name="84715"> </a>The branch cache is automatically cleared by the hardware as part of any instruction-cache invalidate.<b></b></p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84719">Memory Management Unit</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84720"> </a>VxWorks provides two levels of virtual memory support: the basic level bundled with VxWorks, and the full level, unbundled, that requires the optional product VxVMI. These two levels are supported by the MC68040 and MC68060 processors; however, the MC68000, MC68010, and MC68020 processors do not have MMUs.</p><dd><p class="Body"><a name="84724"> </a>For detailed information on VxWorks's MMU support, see <a href="c-vm.html#84369"><i class="title">7. Virtual Memory Interface</i></a>. The following subsections augment the information in that chapter.</p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84728">MC68040 Memory Management Unit</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84729"> </a>On the MC68040, you can set a specific configuration for each memory page. The entire physical memory is described by the data structure <b class="keyword">sysPhysMemDesc[] </b>defined in the BSP file <b class="file">sysLib.c</b>. This data structure is made up of state flags for each page or group of pages. All the state flags defined in <a href="c-vm5.html#84511">Table 7-2</a> of <a href="c-vm.html#84369"><i class="title">7. Virtual Memory Interface</i></a> are available for MC68040 virtual memory pages.</p></dl><dl class="margin"><dd><div class="Item"><a name="85396"> </a><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="85401"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>The <b class="symbol_UC">VM_STATE_CACHEABLE</b> flag listed in <a href="c-vm5.html#84511">Table 7-2</a> of <a href="c-vm.html#84369"><i class="title">7. Virtual Memory Interface</i></a> sets the cache to copyback mode for each page or group of pages.</div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout></div></dl><dl class="margin"><dd><p class="Body"><a name="84753"> </a>In addition, two other state flags are supported:</p></dl><dl class="margin"><ul class="DashSingle" type="circle"><li><a name="84754"> </a><b class="symbol_UC">VM_STATE_CACHEABLE_WRITETHROUGH</b> </li></ul><ul class="DashSingle" type="circle"><li><a name="84755"> </a><b class="symbol_UC">VM_STATE_CACHEABLE_NOT_NON_SERIAL</b> </li></ul></dl><dl class="margin"><dd><p class="Body"><a name="86116"> </a>The first flag sets the page descriptor cache mode field in cacheable writethrough mode, and the second sets it in cache-inhibited non-serialized mode. </p><dd><p class="Body"><a name="86120"> </a>For more information on memory page states, state flags, and state masks, see <a href="c-vm5.html#84502"><i class="title">Page States</i></a>.</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="84766">MC68060 Memory Management Unit</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="84767"> </a>The MMU on the MC68060 is very similar to the MC68040 MMU, and MC68060 virtual memory management provides the same capabilities as the MC68040 virtual memory; see <a href="x-680x04.html#84728"><i class="title">MC68040 Memory Management Unit</i></a> for details.</p><dd><p class="Body"><a name="85904"> </a>You can use the page state constant <b class="symbol_UC">VM_STATE_CACHEABLE_NOT_IMPRECISE </b>instead of <b class="symbol_UC">VM_STATE_CACHEABLE_NOT_NON_SERIAL</b>, to match changes in Motorola terminology (see <a href="x-680x04.html#84682"><i class="title">MC68060 Caches</i></a>). Use this constant (as its name suggests) to set the page descriptor cache mode field to "cache-inhibited imprecise mode." To set the page cache mode to "cache-inhibited precise mode," use <b class="symbol_UC">VM_STATE_CACHEABLE_NOT</b>.</p><dd><p class="Body"><a name="84777"> </a>The MC68060 does not use the data cache when searching MMU address tables, because the MC68060 tablewalker unit has a direct interface to the bus controller. Therefore, virtual address translation tables are always placed in writethrough space. (Although VxWorks maps virtual addresses to the identical physical addresses, the MMU address translation tables also record the page protection provided through VxVMI.)</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84781">Floating-Point Support</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84782"> </a>The MC68020 uses an MC68881/MC68882 floating-point coprocessor for hardware floating-point support. The MC68040 and MC68060 CPUs (but not the MC68LC040) include internal floating-point units that provide a significant subset of the MC68881/MC68882 instruction set, in addition to the same control, status, and data register programming model. Basic floating-point arithmetic and manipulation functions are provided, but higher-level transcendental functions (for example, trigonometric, logarithmic, rounding) are not. Floating-point support for the MC68LC040 is provided in software only.</p><dd><p class="Body"><a name="84784"> </a>Different subsets of the floating-point math routines in <b class="library">mathALib</b> are supported for each processor of the MC680<i class="textVariable">x</i>0 family. <a href="x-680x04.html#84835">Table A-2</a> shows the supported double-precision routines.</p><dd><p class="Body"><a name="84789"> </a>There is no hardware support for single-precision floating-point. On the MC68000, MC68010, MC68020, MC68LC040, and CPU32, software support is available for the following single-precision routines:<p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84792"> </a><b class="routine"><i class="routine">acosf</i></b><b>( )</b></p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84794"> </a><b class="routine"><i class="routine">asinf</i></b><b>( )</b></p>⌨️ 快捷键说明
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