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<td colspan=1 rowspan=1><p class="BodyLeft"><a name="85061"> </a> use write-back cache policy for the page </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85063"> </a><b class="symbol_UC">VM_STATE_WBACK_NOT</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85065"> </a> use write-through cache policy for the page </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85067"> </a><b class="symbol_UC">VM_STATE_GLOBAL</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85069"> </a> set page global bit</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85071"> </a><b class="symbol_UC">VM_STATE_GLOBAL_NOT</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85073"> </a> not set page global bit</p></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p></p><dd><p class="Body"><a name="85074"> </a>Support is provided for two page sizes, 4KB and 4MB. The linear address for 4KB pages is divided into three sections:<p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85077"> </a>Page directory entry </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85079"> </a>bits 22 through 31 </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85081"> </a>Page table entry </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85083"> </a>bits 12 through 21 </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85085"> </a>Page offset </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85087"> </a>bits 0 through 11 </p></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p></p><dd><p class="Body"><a name="85097"> </a>The linear address for 4MB pages is divided into two sections:<p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85090"> </a>Page directory entry </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85092"> </a>bits 22 through 31 </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85094"> </a>Page offset </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85096"> </a>bits 0 through 21 </p></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p></p><dd><p class="Body"><a name="85098"> </a>The page size is configured using <b class="symbol_UC">VM_PAGE_SIZE</b>. The default is 4 KB pages. If you wish to reconfigure 4 MB pages, you must change <b class="symbol_UC">VM_PAGE_SIZE</b> in <b class="file">config.h</b>. (See <a href="c-config.html#84365"><i class="title">8. Configuration and Build</i></a>.) </p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="85099">Global Descriptor Table (GDT)</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="85102"> </a>The GDT is defined as the table <b class="symbol_lc">sysGDT[] </b>in <b class="file">sysALib.s</b>. The table has five entries: a null entry, an entry for program code, an entry for program data, an entry for ISRs, and a reserved entry. It is initially set so that the available memory range is 0x0-0xffffffff. For boards that support PCI, <b class="symbol_UC">INCLUDE_PCI</b> is defined in <b class="file">config.h</b> and VxWorks does not alter the pre-set memory range. This memory range is available at run-time with the MMU configuration.</p><dd><p class="Body"><a name="89661"> </a>If <b class="symbol_UC">INCLUDE_PCI</b> is not defined (the default for boards that do not support PCI), VxWorks adjusts the GDT using the <b class="routine"><i class="routine">sysMemTop</i></b><b>( )</b> routine to check the actual memory size during system initialization and set the table so that the available memory range is 0x0-<b class="symbol_lc">sysMemTop</b>. This causes a General Protection Fault to be generated for any memory access outside the memory range 0x0-<b class="symbol_lc">sysMemTop</b>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="89663">Memory Considerations for VME </a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85108"> </a>The global descriptors for x86 targets are configured for a flat 4GB memory space. </p><dd><p class="Body"><a name="85109"> </a>If you are running VxWorks for the x86 on a VME board, be aware that addressing nonexistent memory or peripherals does not generate a bus error or fault.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85112">Interrupts and Exceptions</a></i></h4></font><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="85113">Interrupt Descriptor Table</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="85115"> </a>The Interrupt Descriptor Table (IDT) occupies the address range 0x0 to 0x800 (also called the Interrupt Vector Table, see <a href="x-ix864.html#88466">Figure D-2</a>). Vector numbers 0x0 to 0x1f are handled by the default exception handler. Vector numbers 0x20 to 0xff are handled by the default interrupt handler.</p><dd><p class="Body"><a name="85119"> </a>By default, vector numbers 0x20 to 0x2f are mapped to IRQ levels 0 to 15. To redefine the base address, edit <b class="symbol_lc">sysVectorIRQ0</b> in <b class="file">sysLib.c</b>. </p><dd><p class="Body"><a name="85121"> </a>For vector numbers 0x0 to 0x11, no task gates are used, only interrupt gates. By default, vector numbers 0x12 to 0xff are trap gates, but this can be changed by redefining the global variable <b class="symbol_lc">sysIntIdtType</b>. </p><dd><p class="Body"><a name="85123"> </a>The difference between an interrupt gate and a trap gate is its effect on the IF flag: using an interrupt gate clears the IF flag, which prevents other interrupts from interfering with the current interrupt handler.</p><dd><p class="Body"><a name="86924"> </a>Each vector of the IDT contains the following information: <p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87930"> </a>offset: </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87932"> </a>offset to the interrupt handler </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87934"> </a>selector:</p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87936"> </a>0x0018, third descriptor (code) in GDT for <br> exception; <br>0x0020, fourth descriptor (code) in GDT for <br> interrupt.</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87938"> </a>descriptor <br> privilege level: </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87940"> </a> <br>3</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87942"> </a>descriptor <br> present bit: </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="87944"> </a> <br>1</p></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p> </p><dd><p class="Body"><a name="85135"> </a>The interrupt handler calls <b class="routine"><i class="routine">intEnt</i></b><b>( )</b> and saves the volatile registers (<b>eax</b>, <b>edx</b>, and <b>ecx</b>). It then calls the ISR, which is usually written in C. Finally, the handler restores the saved registers and calls <b class="routine"><i class="routine">intExit</i></b><b>( )</b>.</p><dd><p class="Body"><a name="85138"> </a>There is no designated interrupt stack. The interrupt's stack frame is built on the interrupted task's stack. Thus, each task requires extra stack space for interrupt nesting; the amount of extra space varies, depending on your ISRs and the potential nesting level.</p><dd><p class="Body"><a name="85139"> </a>Some device drivers (depending on the manufacturer, the configuration, and so on) generate a stray interrupt on IRQ7, which is used by the parallel driver. The global variable <b class="symbol_lc">sysStrayIntCount</b> (see <a href="x-ix865.html#85745">Table D-3</a>) is incremented each time such an interrupt occurs, and a dummy ISR is connected to handle these interrupts.</p><dd><p class="Body"><a name="85144"> </a>The chip generates an exception stack frame in one of two formats, depending on the exception type: (EIP + CS + EFLAGS) or (ERROR + EIP + CS + EFLAGS).</p></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="85145">Machine Check Architecture (MCA)</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="85146"> </a>The Pentium processor introduced a new exception called the machine-check exception (interrupt-18). This exception is used to signal hardware-related errors, such as a parity error on a read cycle. The PentiumPro processor extends the types of errors that can be detected and that generate a machine- check exceptions. It also provides a new machine-check architecture that records information about a machine-check error and provides the basis for an extended error logging capability. </p><dd><p class="Body"><a name="85147"> </a>MCA is enabled and its status registers are set to zero in <b class="routine"><i class="routine">sysHwInit</i></b><b>( )</b>. Its registers are accessed by <b class="routine"><i class="routine">pentiumMsrSet</i></b><b>( )</b> and <b class="routine"><i class="routine">pentiumMsrGet</i></b><b>( )</b>. </p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85149">Registers</a></i></h4></font><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="85150">Memory Type Range Register (MTRR)</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="85151"> </a>MTRR is a feature of the PentiumPro processor that allow the processor to optimize memory operations for different types of memory, such as RAM, ROM, frame buffer memory, and memory-mapped I/O. MTRRs configure an internal map of how physical address ranges are mapped to various types of memory. The processor uses this internal map to determine the cacheability of various physical memory locations and the optimal method of accessing memory locations. </p><dd><p class="Body"><a name="85152"> </a>For example, if a memory location is specified in an MTRR as write-through memory, the processor handles accesses to this location either by reading data from that location in lines and caching the read data or by mapping all writes to that location to the bus and updating the cache to maintain cache coherency. In mapping the physical address space with MTRRs, the processor recognizes five types of memory: uncacheable (UC), write-combining (WC), write-through (WT), write-protected (WP), and write-back (WB).</p><dd><p class="Body"><a name="85153"> </a>The MTRR table is defined as follows:</p><dl class="margin"><dd><pre class="Code2"><b><a name="85154">typedef struct mtrr_fix /* MTRR - fixed range register */ { char type[8]; /* address range: [0]=0-7 ... [7]=56-63 */ } MTRR_FIX; typedef struct mtrr_var /* MTRR - variable range register */ { long long int base; /* base register */ long long int mask; /* mask register */ } MTRR_VAR; typedef struct mtrr /* MTRR */ { int cap[2]; /* MTRR cap register */ int deftype[2]; /* MTRR defType register */ MTRR_FIX fix[11]; /* MTRR fixed range registers */ MTRR_VAR var[8]; /* MTRR variable range registers */ } MTRR;</a></b></pre></dl></dl><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="85155">Model Specific Register (MSR)</a></i></h5></font><dl class="margin">⌨️ 快捷键说明
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