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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> Intel x86 </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="x-ix86.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="x-ix863.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="x-ix865.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="84946">D.4 Architecture Considerations</a></i></h3></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84947"> </a>This section describes the following characteristics of the Intel x86 architectures that you should keep in mind as you write a VxWorks application:</p></dl><dl class="margin"><ul class="BulletSingle" type="disc"><li><a name="84948"> </a>Operating mode, privilege protection, and byte order </li></ul><ul class="BulletSingle" type="disc"><li><a name="84949"> </a>Memory segmentation and the MMU </li></ul><ul class="BulletSingle" type="disc"><li><a name="84950"> </a>I/O and memory mapped devices </li></ul><ul class="BulletSingle" type="disc"><li><a name="84951"> </a>Memory considerations for VME </li></ul><ul class="BulletSingle" type="disc"><li><a name="84952"> </a>Interrupts and exceptions </li></ul><ul class="BulletSingle" type="disc"><li><a name="84953"> </a>Registers</li></ul><ul class="BulletSingle" type="disc"><li><a name="84954"> </a>Counters</li></ul><ul class="BulletSingle" type="disc"><li><a name="84955"> </a>Context switching </li></ul><ul class="BulletSingle" type="disc"><li><a name="84956"> </a>ISA/EISA bus </li></ul><ul class="BulletSingle" type="disc"><li><a name="84957"> </a>PC104 bus </li></ul><ul class="BulletSingle" type="disc"><li><a name="84958"> </a>PCI bus </li></ul><ul class="BulletSingle" type="disc"><li><a name="84959"> </a>Software floating-point emulation </li></ul><ul class="BulletSingle" type="disc"><li><a name="84960"> </a>VxWorks memory layout </li></ul></dl><dl class="margin"><dd><p class="Body"><a name="84961"> </a>Consult Intel's <i class="title">Intel486 Microprocessor Family Programmer's Reference Manual</i> for details on the x86 architectures.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84963">Operating Mode, Privilege Protection, and Byte Order</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84964"> </a>VxWorks for the x86 runs in the 32-bit protected mode.</p><dd><p class="Body"><a name="84965"> </a>No privilege protection is used, thus there are no call gates. The privilege level is always 0, the most privileged level (Supervisor mode).</p><dd><p class="Body"><a name="84967"> </a>The x86 <b></b>byte order is little-endian, but network applications must convert some data to a standard network order, which is big-endian. In particular, in network applications, be sure to convert the port number to network byte order using <b class="routine"><i class="routine">htons</i></b><b>( )</b>.</p><dd><p class="Body"><a name="84968"> </a>See <i class="title">VxWorks Network Programmer's Guide: TCP/IP under VxWorks </i>for more information about macros and routines to convert byte order (from little-endian to big-endian or vice versa). </p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84971">Memory Segmentation</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84972"> </a>The Intel x86 processors support both I/O-mapped devices and memory-mapped devices.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="84974">I/O Mapped Devices</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="84975"> </a>For I/O mapped devices, developers may use the following routines from <i class="textVariable">installDir</i><b class="file">/target/config/</b><i class="textVariable">bspName</i><b class="file">/sysALib.s</b>:<p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84979"> </a><b class="routine"><i class="routine">sysInByte</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84981"> </a>- input one byte from I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84984"> </a><b class="routine"><i class="routine">sysOutByte</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84986"> </a>- output one byte to I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84989"> </a><b class="routine"><i class="routine">sysInWord</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84991"> </a>- input one word from I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84994"> </a><b class="routine"><i class="routine">sysOutWord</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84996"> </a>- output one word to I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="84999"> </a><b class="routine"><i class="routine">sysInLong</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85001"> </a>- input one long word from I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85004"> </a><b class="routine"><i class="routine">sysOutLong</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85006"> </a>- output one long word to I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85009"> </a><b class="routine"><i class="routine">sysInWordString</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85011"> </a>- input a word string from I/O space</p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85014"> </a><b class="routine"><i class="routine">sysOutWordString</i></b><b>( )</b></p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85016"> </a>- output a word string to I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85019"> </a><b class="routine"><i class="routine">sysInLongString</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85021"> </a>- input a long string from I/O space </p></td></tr><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85024"> </a><b class="routine"><i class="routine">sysOutLongString</i></b><b>( )</b> </p></td><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85026"> </a>- output a long string to I/O space </p></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p></p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H4"><i><a name="85028">Memory Mapped Devices</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85029"> </a>For memory mapped devices, there are two kinds of memory protection provided by VxWorks: the Memory Management Unit and the Global Descriptor Table. Because VxWorks operates at the highest processor privilege level, no "protection rings" exist.</p><dd><p class="Body"><a name="85030"> </a>The x86 processors allow you to configure the memory space into valid and invalid areas, even under Supervisor mode. Thus, you receive a page fault only if the processor attempts to access addresses mapped as invalid, or addresses that have not been mapped. Conversely, if the processor attempts to access a nonexistent address space that has been mapped as valid, no page fault occurs.</p></dl></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="85031">Memory Management Unit (MMU)</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="85034"> </a>If <b class="symbol_UC">INCLUDE_MMU_BASIC</b> is selected for inclusion in the project facility VxWorks view, then VxWorks enables the MMU with the <b class="symbol_lc">mmuPhysDesc[]</b> table which includes PCI memory mapping information. This is the default.</p><dd><p class="Body"><a name="85036"> </a>If you have other memory mapped devices and if <b class="symbol_UC">INCLUDE_MMU_BASIC</b> is included (the default), you may need to add your device address space into the MMU table by manually editing the MMU configuration structure <b class="symbol_lc">sysPhysMemDesc[]</b> in <b class="file">sysLib.c</b>. For information on editing the <b class="symbol_lc">sysPhysMemDesc[]</b> structure, see <a href="c-vm3.html#84391"><i class="title">7.3 Virtual Memory Configuration</i></a>. Do not overlap any existing MMU entries, and be sure all entries are page aligned. We recommend that you also maintain a 1:1 correlation between virtual and physical memory, since VxWorks and all tasks use a common address space.</p><dd><p class="Body"><a name="85041"> </a>Attempts to access areas not mapped as valid in the MMU result in page faults.</p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="86623"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>The i386 MMU does not have write-protect capability.</div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout></dl><dl class="margin"><dd><font face="Helvetica, sans-serif" size="-1" class="sans"><h5 class="HU"><i><a name="86639">PentiumPro MMU</a></i></h5></font><dl class="margin"><dd><p class="Body"><a name="85053"> </a>PentiumPro's enhanced MMU supports two additional page attribute bits. </p><dd><p class="Body"><a name="85054"> </a>The global bit (G) indicates a global page when set. When a page is marked global and the page global enable (PGE) bit in register CR4 is set, the page-table or page-directory entry for the page is not invalidated in the TLB when register CR3 is loaded or a task switch occurs. This bit is provided to prevent frequently used pages (such as pages that contain kernel or other operating system or executive code) from being flushed from the TLB.</p><dd><p class="Body"><a name="85055"> </a>The page-level write-through/back bit (PWT) controls the write-through or write- back caching policy of individual pages or page tables. When the PWT bit is set, write-through caching is enabled for the associated page or page table. When the bit is clear, write-back caching is enabled for the associated page and page table.</p><dd><p class="Body"><a name="85056"> </a>The following macros describe these attribute bits in the physical memory descriptor table <b class="symbol_lc">sysPhysMemDesc[]</b> in <b class="file">sysLib.c</b>.<p class="table"><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td colspan=1 rowspan=1><p class="BodyLeft"><a name="85059"> </a><b class="symbol_UC">VM_STATE_WBACK</b> </p></td>⌨️ 快捷键说明
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