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this about vxworks operations systems

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<p class="BodyLeft"><a name="84770"> </a><b class="routine"><i class="routine">sin</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="84772"> </a><b class="routine"><i class="routine">sqrt</i></b><b>(&nbsp;)</b> </p>

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<dd><p class="Body"><a name="86101"> </a>The following floating-point functions are not available on PowerPC 60X processors: <p class="table">
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<p class="BodyLeft"><a name="86105"> </a><b class="routine"><i class="routine">cbrt</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86107"> </a><b class="routine"><i class="routine">infinity</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86109"> </a><b class="routine"><i class="routine">irint</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86111"> </a><b class="routine"><i class="routine">iround</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86113"> </a><b class="routine"><i class="routine">log2</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86115"> </a><b class="routine"><i class="routine">round</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86117"> </a><b class="routine"><i class="routine">sincos</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86119"> </a><b class="routine"><i class="routine">trunc</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86121"> </a><b class="routine"><i class="routine">trunc</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86123"> </a><b class="routine"><i class="routine">sin</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86125"> </a><b class="routine"><i class="routine">sqrt</i></b><b>(&nbsp;)</b> </p>

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<p class="BodyLeft"><a name="86127"> </a></p>

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<dd><p class="Body"><a name="86181"> </a>No single-precision functions are available for 60X processors.</p>
<dd><p class="Body"><a name="84776"> </a>Handling of floating-point exceptions is supported for PowerPC 60X processors. By default the floating-point exceptions are disabled.</p>
<dd><p class="Body"><a name="84780"> </a>To change the default for a task spawned with the <b class="symbol_UC">VX_FP_TASK</b> option, modify the values of the Machine State Register (MSR) and the Floating Point Status and Control Register (FPSCR) at the beginning of the task code.</p>
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<ul class="Dash" type="circle"><li><a name="84781"> </a>The MSR's FE0 and FE1 bits select the floating-point exception mode.</li></ul>
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<ul class="Dash" type="circle"><li><a name="84782"> </a>The FPSCR's VE, OE, UE, ZE, XE, NI, and RN bits enable or disable the corresponding floating-point exceptions and rounding mode. (See <b class="file">archPpc.h</b> for the macros <b class="symbol_UC">PPC_FPSCR_VE</b> and so forth.)</li></ul>
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<dd><p class="Body"><a name="84783"> </a>Register values may be accessed by the routines <b class="routine"><i class="routine">vxMsrGet</i></b><b>(&nbsp;)</b>, <b class="routine"><i class="routine">vxMsrSet</i></b><b>(&nbsp;)</b>, <b class="routine"><i class="routine">vxFpscrGet</i></b><b>(&nbsp;)</b>, and <b class="routine"><i class="routine">vxFpscrSet</i></b><b>(&nbsp;)</b>.</p>
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<h4 class="H4"><i><a name="84785">VxMP Support for Motorola PowerPC Boards</a></i></h4>
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<dd><p class="Body"><a name="84786"> </a>VxMP is an optional VxWorks component that provides shared-memory objects dedicated to high-speed synchronization and communication between tasks running on separate CPUs. For complete documentation of the optional component VxMP, see <a href="c-smo.html#84368"><i class="title">6.&nbsp;Shared-Memory Objects</i></a>.</p>
<dd><p class="Body"><a name="84790"> </a>Normally, boards that make use of VxMP must support hardware test-and-set (<i class="term">TAS</i>: atomic read-modify-write cycle). Motorola PowerPC boards do not provide atomic (indivisible) TAS as a hardware function. VxMP for PowerPC provides special software routines which allow these Motorola boards to make use of VxMP.</p>
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<h5 class="HU"><i><a name="84791">Boards Affected</a></i></h5>
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<dd><p class="Body"><a name="84792"> </a>The current release of VxMP provides a software implementation of a hardware TAS for PowerPC-based VME boards of the 1300, 1600, and 2600 families manufactured by Motorola. No other PowerPC boards are affected.</p>
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<hr><div class="CalloutCell"><a name="85028"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">NOTE:  </font></b></a>Some PowerPC board manufacturers, for example Cetia, claim to equip their boards with hardware support for true atomic operations over the VME bus. Such boards do not need the special software written for the Motorola boards.</div>
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<h5 class="HU"><i><a name="84802">Implementation</a></i></h5>
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<dd><p class="Body"><a name="84803"> </a>The VxMP product for Motorola PowerPC boards has special software routines which compensate for the lack of atomic TAS operations in the PowerPC and the lack of atomic instruction propagation to and from these boards. This software consists of the routines <b class="routine"><i class="routine">sysBusTas</i></b><b>(&nbsp;)</b> and <b class="routine"><i class="routine">sysBusTasClear</i></b><b>(&nbsp;)</b>.</p>
<dd><p class="Body"><a name="84804"> </a>The software implementation uses ownership of the VME bus as a semaphore; in other words, no TAS operation can be performed by a task until that task owns the VME bus. When the TAS operation completes, the VME bus is released. This method is similar to the special read-modify-write cycle on the VME bus in which the bus is owned implicitly by the task issuing a TAS instruction. (This is the hardware implementation employed, for example, with a 68K processor.) However, the software implementation comes at a price. Execution is slower because, unlike true atomic instructions, <b class="routine"><i class="routine">sysBusTas</i></b><b>(&nbsp;)</b> and <b class="routine"><i class="routine">sysBusTasClear</i></b><b>(&nbsp;)</b> require many clock cycles to complete.</p>
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<h5 class="HU"><i><a name="84805">Configuring Hardware TAS</a></i></h5>
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<dd><p class="Body"><a name="84808"> </a>To invoke this feature, set <b class="symbol_UC">SM_TAS_TYPE</b> to <b class="symbol_UC">SM_TAS_HARD</b> on the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab of the project facility under <b class="symbol_UC">INCLUDE_SM_OBJ</b>.</p>
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<h5 class="HU"><i><a name="84809">Restrictions for Multi-Board Configurations</a></i></h5>
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<dd><p class="Body"><a name="84810"> </a>Systems using multiple VME boards where at least one board is a Motorola PowerPC board must have a Motorola PowerPC board as the board with a processor ID equal to 0 (the board whose memory is allocated and shared). This is because a TAS operation on local memory by, for example, a 68K processor does not involve VME bus ownership and is, therefore, not atomic as seen from a Motorola PowerPC board. </p>
<dd><p class="Body"><a name="84811"> </a>This restriction does not apply to systems that have globally shared memory boards which are used for shared memory operations. Specifying <b class="symbol_UC">SM_OFF_BOARD</b> as TRUE on the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab of the properties window for the processor with ID of 0 and setting the associated parameters will enable you to assign processor IDs in any configuration. (See <b><i><a href="c-smo4.html#85430"></i></b><i class="title">6.4.3&nbsp;Initializing the Shared-Memory Objects Package</i><b><i></a></i></b>.) <b><i></i></b></p>
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<h4 class="H4"><i><a name="84814">Memory Layout</a></i></h4>
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<dd><p class="Body"><a name="85375"> </a>The VxWorks memory layout is the same for all PowerPC processors. <a href="x-ppc4.html#85401">Figure&nbsp;F-1</a> shows the memory layout, labeled as follows:<p class="table">

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<p class="BodyLeft"><a name="85753"> </a>Interrupt Vector Table </p>

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<p class="BodyLeft"><a name="85755"> </a>Table of exception/interrupt vectors.</p>

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<p class="BodyLeft"><a name="85757"> </a>SM Anchor </p>

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<p class="BodyLeft"><a name="85759"> </a>Anchor for the shared memory network and VxMP shared memory objects (if there is shared memory on the board).</p>

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<p class="BodyLeft"><a name="85761"> </a>Boot Line </p>

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<p class="BodyLeft"><a name="85763"> </a>ASCII string of boot parameters.</p>

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<p class="BodyLeft"><a name="85765"> </a>Exception Message </p>

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<p class="BodyLeft"><a name="85767"> </a>ASCII string of the fatal exception message.</p>

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<p class="BodyLeft"><a name="85769"> </a>Initial Stack </p>

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<p class="BodyLeft"><a name="85771"> </a>Initial stack for <b class="routine"><i class="routine">usrInit</i></b><b>(&nbsp;)</b>, until <b class="routine"><i class="routine">usrRoot</i></b><b>(&nbsp;)</b> gets allocated stack.</p>

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<p class="BodyLeft"><a name="85773"> </a>System Image </p>

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<p class="BodyLeft"><a name="85775"> </a>VxWorks itself (three sections: text, data, bss). The entry point for VxWorks is at the start of this region, which is BSP dependent. The entry point for each BSP is as follows:</p>

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<p class="BodyLeft"><a name="85777"> </a></p>

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<p class="BodyLeft"><a name="85779"> </a>cetCvme604: &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;0x100,000</p>

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<p class="BodyLeft"><a name="85781"> </a></p>

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<p class="BodyLeft"><a name="85783"> </a>evb403, ads850: &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;0x10,000 </p>

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<p class="BodyLeft"><a name="85785"> </a></p>

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<p class="BodyLeft"><a name="85787"> </a>mv1603/4: &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;0x30,000 </p>

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<p class="BodyLeft"><a name="85791"> </a>ultra60X: &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;0x10,000</p>

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<p class="BodyLeft"><a name="85793"> </a>Host Memory Pool </p>

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<p class="BodyLeft"><a name="85795"> </a>Memory allocated by host tools. The size depends on the the macro <b class="symbol_UC">WDB_POOL_SIZE</b>. Modify <b class="symbol_UC">WDB_POOL_SIZE</b> under <b class="symbol_UC">INCLUDE_WDB</b>.</p>

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<p class="BodyLeft"><a name="85797"> </a>Interrupt Stack </p>

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<p class="BodyLeft"><a name="85799"> </a>Size is defined by <b class="symbol_UC">ISR_STACK_SIZE</b> under <b class="symbol_UC">INCLUDE_KERNEL</b>. Location depends on system image size.</p>

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<p class="BodyLeft"><a name="85801"> </a>System Memory Pool </p>

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<p class="BodyLeft"><a name="85803"> </a>Size depends on the size of the system image. The <b class="routine"><i class="routine">sysMemTop</i></b><b>(&nbsp;)</b><b class="routine"><i class="routine"> </i></b>routine returns the address of the end of the free memory pool.</p>

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<dd><p class="Body"><a name="85393"> </a>All addresses shown in <a href="x-ppc4.html#85401">Figure&nbsp;F-1</a> are relative to the start of memory for a particular target board. The start of memory (corresponding to 0x0 in the memory-layout diagram) is defined as <b class="symbol_UC">LOCAL_MEM_LOCAL_ADRS</b> under <b class="symbol_UC">INCLUDE_MEMORY_CONFIG</b> for each target.<div class="frame">
<h4 class="EntityTitle"><a name="85401"><font face="Helvetica, sans-serif" size="-1" class="sans">Figure F-1:&nbsp;&nbsp;VxWorks System Memory Layout (PowerPC)</font></a></h4>

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<p class="FootnoteNumberMarker">1:&nbsp;
<span class="Footnote"><a name="86289"> </a>W:    the <b class="symbol_UC">WRITETHROUGH</b> or <b class="symbol_UC">COPYBACK</b> attribute.</span>
<span class="Footnote"><a name="86290"> </a>        I:                the inhibited attribute.</span>
<span class="Footnote"><a name="86291"> </a>        M:    the memory coherency attribute</span>
<span class="Footnote"><a name="86292"> </a>        G:    the guarded attribute</span>

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