alu.vhd

vhdl 语言程序设计

Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;

Entity alu is 
  generic (size: integer:=4);
 port (
       a: in std_logic_vector (size-1 downto 0);
       b: in std_logic_vector ( size-1 downto 0);
       ctrl: in std_logic_vector (1 downto 0);
       q: out std_logic_vector (size-1 downto 0);
       cout: out std_logic);
 End alu;
 
 Architecture structal of alu is 
 
  Component nandgate 
     port ( in1: in std_logic_vector ( size-1 downto 0);
            in2: in std_logic_vector ( size-1 downto 0);
            q:   out std_logic_vector ( size-1 downto 0));
  End component;
  
   Component norgate
     port ( in1: in std_logic_vector ( size-1 downto 0);
            in2: in std_logic_vector ( size-1 downto 0);
            q:   out std_logic_vector ( size-1 downto 0));
   End component;
   
   Component mux
       Port ( in1, in2, in3: in std_logic_vector ( size-1 downto 0);
        ctrl: in std_logic_vector ( 1 downto 0);
        q:    out  std_logic_vector ( size-1 downto 0));
   End component;
   
   Component addsubtractor 
        Port (in1, in2: in std_logic_vector ( size-1 downto 0);
        ctrl:     in std_logic_vector ( 1 downto 0);
        sum:      out std_logic_vector ( size-1 downto 0);
        cout:     out std_logic);
   End component;
   
   Signal c1,c2,c3: std_logic_vector ( size-1 downto 0);
   
   Begin
    u1: nandgate port map (a,b,c1);
    u2: norgate  port map (a,b,c2);
    u3: addsubtractor port map (a,b,ctrl,c3,cout);
    u4: mux      port map  (c3,c2,c1,ctrl,q);

    
  End structal;