alu.cr.mti

vhdl 语言程序设计

{E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity testbench
-- Compiling architecture test of testbench

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/norgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/norgate.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity norgate
-- Compiling architecture dataflow of norgate

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/alu.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/alu.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity alu
-- Compiling architecture structal of alu

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd} {0 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Compiling entity addsubtractor
-- Compiling architecture behavior of addsubtractor
** Error: E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd(33): No feasible entries for infix operator "+".
** Error: E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd(33): Bad right hand side (infix expression) in variable assignment.
** Warning: [2] E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd(42): (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
** Error: E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd(16): Variable declaration 'carry' not allowed in this region.
** Error: E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd(17): Variable declaration 'sum1' not allowed in this region.
** Error: E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd(18): Variable declaration 'notin2' not allowed in this region.
** Error: E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd(43): VHDL Compiler exiting

} {10.0 12.0 13.0 17.0} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/mux.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/mux.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity mux
-- Compiling architecture dataflow of mux

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/nandgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/nandgate.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity nandgate
-- Compiling architecture dataflow of nandgate

} {} {}}