alu1.cr.mti

来自「vhdl 语言程序设计」· MTI 代码 · 共 58 行

{E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity testbench
-- Compiling architecture test of testbench

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/norgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/norgate.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Compiling entity norgate
-- Compiling architecture dataflow of norgate

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/alu.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/alu.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Compiling entity alu
-- Compiling architecture structal of alu

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/nandgate.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/nandgate.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Compiling entity nandgate
-- Compiling architecture dataflow of nandgate

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/mux.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/mux.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Compiling entity mux
-- Compiling architecture dataflow of mux

} {} {}} {E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd} {1 {vcom -work work -2002 -explicit {E:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Compiling entity addsubtractor
-- Compiling architecture behavior of addsubtractor

} {} {}}