_info

vhdl 语言程序设计

m255
13
cModel Technology
dE:\SOC\VHDL\Lab\Lab 1\ALU
Eaddsub
w1157678538
FE:/SOC/VHDL/Lab/Lab 1/lab1/addSub.vhd
l0
L1
VHbO<b[DTF73M9bX`PeNRP1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Aaddsubn
DE work fulladder_one 50mYNX1==`e2Kb982XdHW0
DE work addsub HbO<b[DTF73M9bX`PeNRP1
l20
L11
V7QRlHG9BHe>D`AEYidodz3
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Eaddsubtractor
w1157655635
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FE:/SOC/VHDL/Lab/Lab 1/ALU/addsubtractor.vhd
l0
L8
VKBlXAokVJKdQ^O_l7:B`k1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehavior
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work addsubtractor KBlXAokVJKdQ^O_l7:B`k1
l17
L16
VHAaA>ZT<SU`o1OeCjbe>92
OE;C;6.0;29
32
M4 ieee std_logic_1164
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 ieee numeric_std
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Ealu
w1157678920
FE:/SOC/VHDL/Lab/Lab 1/lab1/alu.vhd
l0
L2
VGIN:YNAB]0Ei89PNREEfd3
OE;C;6.0;29
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o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Aam
DE work norgate RZc6^h=9oW6GKanCH2;JC0
DE work nandgate WU``?z0?9mUSMid4Uio_C2
DE work addsub HbO<b[DTF73M9bX`PeNRP1
DE work alu GIN:YNAB]0Ei89PNREEfd3
l50
L14
VhjWeYOoXJM03U`H_`6ejW1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Astructal
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work alu FLhMQFGJLTJjGaC?oRK=Z1
l46
L17
VUKMGAk52FZnHP5znHWjGU3
OE;C;6.0;29
32
M4 ieee std_logic_1164
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 ieee numeric_std
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
FE:/SOC/VHDL/Lab/Lab 1/ALU/alu.vhd
w1157661202
Efulladder_one
w1157677620
FE:/SOC/VHDL/Lab/Lab 1/lab1/fulladder_one.vhd
l0
L1
V50mYNX1==`e2Kb982XdHW0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Amac
DE work fulladder_one 50mYNX1==`e2Kb982XdHW0
l9
L8
VPazHl8KHcjd0JJN76Z4zA2
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Emux
w1157652933
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FE:/SOC/VHDL/Lab/Lab 1/ALU/mux.vhd
l0
L7
VW1>d:KZe:B1[eATbn^_Km1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Adataflow
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work mux W1>d:KZe:B1[eATbn^_Km1
l14
L13
V_<SG0M`FcLYflF0j`eBd51
OE;C;6.0;29
32
M4 ieee std_logic_1164
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 ieee numeric_std
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Enandgate
w1157677598
FE:/SOC/VHDL/Lab/Lab 1/lab1/nandgate.vhd
l0
L1
VWU``?z0?9mUSMid4Uio_C2
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Adataflow
DE work nandgate WU``?z0?9mUSMid4Uio_C2
l14
L10
V2W``OjDCLAmEJOMMCNn>?2
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Enorgate
w1157677608
FE:/SOC/VHDL/Lab/Lab 1/lab1/norgate.vhd
l0
L1
VRZc6^h=9oW6GKanCH2;JC0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Adataflow
DE work norgate RZc6^h=9oW6GKanCH2;JC0
l14
L10
V:<:=MK:iYQ>T2acn3?8Uj3
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Etest
w1063087944
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
FE:/SOC/VHDL/Lab/Lab 1/lab1/tb_alu.vhd
l0
L6
VYjh;BOmXX8Fc5`VR?F[IG0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Atb_alu
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work test Yjh;BOmXX8Fc5`VR?F[IG0
l66
L8
V_j=obLbNgJfhEKDFBdRbM2
OE;C;6.0;29
32
M2 ieee std_logic_1164
M1 ieee numeric_std
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Atestbench
DE work test 9>5BV[_SiJ8o9P6LEh=Q^2
l13
L5
Vz6eP3N@4N^B;K_PzB;YgH0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
FE:/SOC/VHDL/Lab/Lab 1/ALU/testbanch .vhd
w1157553755
Etestbench
w1157617529
FE:/SOC/VHDL/Lab/Lab 1/ALU/testbench of nandgate.vhd
l0
L1
V>;b4LRla6Ue<A[OBJm00H0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Atest
DE work testbench >;b4LRla6Ue<A[OBJm00H0
l11
L3
V4F8EP`z@TZz?>eTbYE^o40
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000