nandgate.vhd.bak

vhdl 语言程序设计

Entity nandgate is 
 generic (size: integer:=4); 
 port ( in1: in std_logic_vector ( size-1 downto 0);
        in2: in std_logic_vector( size-1 downto 0);
        q:   out std_logic_vector( size-1 downto 0));
End nandgate;

Architecture dataflow of nandgate is 
signal q1: std_logic_vector ( size-1 downto 0);
begin
    q1<= in1 and in2;
    q<= not q1;
end dataflow;