bamboo.h

gec2410上的u-boot-1.2.0源码

/*
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*----------------------------------------------------------------------------+
  | FPGA registers and bit definitions
  +----------------------------------------------------------------------------*/
/*
 * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
 * TLB initialization makes it correspond to logical address 0x80001FF0.
 * => Done init_chip.s in bootlib
 */
#define FPGA_BASE_ADDR	0x80002000

/*----------------------------------------------------------------------------+
  | Board Jumpers Setting Register
  |   Board Settings provided by jumpers
  +----------------------------------------------------------------------------*/
#define FPGA_SETTING_REG	    (FPGA_BASE_ADDR+0x3)
/* Boot from small flash */
#define	    FPGA_SET_REG_BOOT_SMALL_FLASH	    0x80
/* Operational Flash versus SRAM position in Memory Map */
#define	    FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK	    0x40
#define	     FPGA_SET_REG_OP_CODE_FLASH_ABOVE	     0x40
#define	     FPGA_SET_REG_SRAM_ABOVE		     0x00
/* Boot From NAND Flash */
#define	    FPGA_SET_REG_BOOT_NAND_FLASH_MASK	    0x40
#define	    FPGA_SET_REG_BOOT_NAND_FLASH_SELECT	     0x00
/* On Board PCI Arbiter Select */
#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK   0x10
#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL	    0x00

/*----------------------------------------------------------------------------+
  | Functions Selection Register 1
  +----------------------------------------------------------------------------*/
#define FPGA_SELECTION_1_REG	    (FPGA_BASE_ADDR+0x4)
#define	    FPGA_SEL_1_REG_PHY_MASK	    0xE0
#define	    FPGA_SEL_1_REG_MII		    0x80
#define	    FPGA_SEL_1_REG_RMII		    0x40
#define	    FPGA_SEL_1_REG_SMII		    0x20
#define	    FPGA_SEL_1_REG_USB2_DEV_SEL	    0x10	   /* USB2 Device Selection */
#define	    FPGA_SEL_1_REG_USB2_HOST_SEL    0x08	   /* USB2 Host Selection */
#define	    FPGA_SEL_1_REG_NF_SELEC_MASK    0x07	   /* NF Selection Mask */
#define	    FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04	   /* NF0 Selected by NF_CS1 */
#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02	   /* NF1 Selected by NF_CS2 */
#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01	   /* NF1 Selected by NF_CS3 */

/*----------------------------------------------------------------------------+
  | Functions Selection Register 2
  +----------------------------------------------------------------------------*/
#define FPGA_SELECTION_2_REG	    (FPGA_BASE_ADDR+0x5)
#define	    FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80	   /* IIC1 / SCP Selection */
#define	    FPGA_SEL2_REG_SEL_FRAM	    0x80	   /* FRAM on IIC1 bus selected - SCP Select */
#define	    FPGA_SEL2_REG_SEL_SCP	    0x80	   /* Identical to SCP Selection */
#define	    FPGA_SEL2_REG_SEL_IIC1	    0x00	   /* IIC1 Selection - Default Value */
#define	    FPGA_SEL2_REG_SEL_DMA_A_B	    0x40	   /* DMA A & B channels selected */
#define	    FPGA_SEL2_REG_SEL_DMA_C_D	    0x20	   /* DMA C & D channels selected */
#define	    FPGA_SEL2_REG_DMA_EOT_TC_3_SEL  0x10	   /* 0 = EOT - input to 440EP */
							   /* 1 = TC - output from 440EP */
#define	    FPGA_SEL2_REG_DMA_EOT_TC_2_SEL  0x08	   /* 0 = EOT (input to 440EP) */
							   /* 1 = TC (output from 440EP) */
#define	    FPGA_SEL2_REG_SEL_GPIO_1	    0x04	   /* EBC_GPIO & USB2_GPIO selected */
#define	    FPGA_SEL2_REG_SEL_GPIO_2	    0x02	   /* Ether._GPIO & UART_GPIO selected */
#define	    FPGA_SEL2_REG_SEL_GPIO_3	    0x01	   /* DMA_GPIO & Trace_GPIO selected */

/*----------------------------------------------------------------------------+
  | Functions Selection Register 3
  +----------------------------------------------------------------------------*/
#define FPGA_SELECTION_3_REG	    (FPGA_BASE_ADDR+0x6)
#define	    FPGA_SEL3_REG_EXP_SLOT_EN		    0x80    /* Expansion Slot enabled */
#define	    FPGA_SEL3_REG_SEL_UART_CONFIG_MASK	    0x70
#define	    FPGA_SEL3_REG_SEL_UART_CONFIG1	    0x40    /* one 8_pin UART */
#define	    FPGA_SEL3_REG_SEL_UART_CONFIG2	    0x20    /* two 4_pin UARTs */
#define	    FPGA_SEL3_REG_SEL_UART_CONFIG3	    0x10    /* one 4_pin & two 2_pin UARTs */
#define	    FPGA_SEL3_REG_SEL_UART_CONFIG4	    0x08    /* four 2_pin UARTs */
#define	    FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART   0x00    /* DTR/DSR mode for 4_pin_UART */
#define	    FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART   0x04    /* RTS/CTS mode for 4_pin_UART */

/*----------------------------------------------------------------------------+
  | Soft Reset Register
  +----------------------------------------------------------------------------*/
#define FPGA_RESET_REG		    (FPGA_BASE_ADDR+0x7)
#define	    FPGA_RESET_REG_RESET_USB20_DEV	    0x80    /* Hard Reset of the GT3200 */
#define	    FPGA_RESET_REG_RESET_DISPLAY	    0x40    /* Hard Reset on Display Device */
#define	    FPGA_RESET_REG_STATUS_LED_0		    0x08    /* 1 = Led On */
#define	    FPGA_RESET_REG_STATUS_LED_1		    0x04    /* 1 = Led On */
#define	    FPGA_RESET_REG_STATUS_LED_2		    0x02    /* 1 = Led On */
#define	    FPGA_RESET_REG_STATUS_LED_3		    0x01    /* 1 = Led On */


/*----------------------------------------------------------------------------+
| SDR Configuration registers
+----------------------------------------------------------------------------*/
/* Serial Device Strap Reg 0 */
#define SDR0_SDSTP0		     0x0020
/* Serial Device Strap Reg 1 */
#define SDR0_SDSTP1		     0x0021
/* Serial Device Strap Reg 2 */
#define SDR0_SDSTP2		     SDR0_STRP2
/* Serial Device Strap Reg 3 */
#define SDR0_SDSTP3		     SDR0_STRP3

#define sdr_pstrp0		     0x0040

#define	  SDR0_SDSTP1_EBC_ROM_BS_MASK  0x00006000  /* EBC Boot Size Mask */
#define	  SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000    /* EBC 32 bits */
#define	  SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000    /* EBC 16 Bits */
#define	  SDR0_SDSTP1_EBC_ROM_BS_8BIT  0x00000000    /* EBC  8 Bits */

#define	  SDR0_SDSTP1_BOOT_SEL_MASK    0x00001800   /* Boot device Selection Mask */
#define	  SDR0_SDSTP1_BOOT_SEL_EBC     0x00000000     /* EBC */
#define	  SDR0_SDSTP1_BOOT_SEL_PCI     0x00000800     /* PCI */
#define	  SDR0_SDSTP1_BOOT_SEL_NDFC    0x00001000     /* NDFC */

/* Serial Device Enabled - Addr = 0xA8 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
/* Serial Device Enabled - Addr = 0xA4 */
#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7

/* Pin Straps Reg */
#define SDR0_PSTRP0		     0x0040
#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */

#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000  /* Default strap settings 0 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000  /* Default strap settings 1 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000  /* Default strap settings 2 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000  /* Default strap settings 3 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000  /* Default strap settings 4 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000  /* Default strap settings 5 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000  /* Default strap settings 6 */
#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000  /* Default strap settings 7 */

/*----------------------------------------------------------------------------+
| EBC Configuration Register - EBC0_CFG
+----------------------------------------------------------------------------*/
/* External Bus Three-State Control */
#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
/* Device-Paced Time-out Disable */
#define EBC0_CFG_PTD_ENABLED	    0x00000000
/* Ready Timeout Count */
#define EBC0_CFG_RTC_MASK	    0x38000000
#define EBC0_CFG_RTC_16PERCLK	    0x00000000
#define EBC0_CFG_RTC_32PERCLK	    0x08000000
#define EBC0_CFG_RTC_64PERCLK	    0x10000000
#define EBC0_CFG_RTC_128PERCLK	    0x18000000
#define EBC0_CFG_RTC_256PERCLK	    0x20000000
#define EBC0_CFG_RTC_512PERCLK	    0x28000000
#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
/* External Master Priority Low */
#define EBC0_CFG_EMPL_LOW	    0x00000000
#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
#define EBC0_CFG_EMPL_HIGH	    0x06000000
/* External Master Priority High */
#define EBC0_CFG_EMPH_LOW	    0x00000000
#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
#define EBC0_CFG_EMPH_HIGH	    0x01800000
/* Chip Select Three-State Control */
#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
/* Burst Prefetch */
#define EBC0_CFG_BPF_ONEDW	    0x00000000
#define EBC0_CFG_BPF_TWODW	    0x00100000
#define EBC0_CFG_BPF_FOURDW	    0x00200000
/* External Master Size */
#define EBC0_CFG_EMS_8BIT	    0x00000000
/* Power Management Enable */
#define EBC0_CFG_PME_DISABLED	    0x00000000
#define EBC0_CFG_PME_ENABLED	    0x00020000
/* Power Management Timer */
#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)

/*----------------------------------------------------------------------------+
| Peripheral Bank Configuration Register - EBC0_BnCR
+----------------------------------------------------------------------------*/