hal_xc_auto.h

gec2410上的u-boot-1.2.0源码

/* ****************************************************************
 * Common defs for reg spec for chip xc
 * Auto-generated by trex2: DO NOT HAND-EDIT!!
 * ****************************************************************
 */

#ifndef HAL_XC_AUTO_H
#define HAL_XC_AUTO_H

/* ----------------------------------------------------------------
 * For block: 'xcvr_cntl'
 */

/* ---- Block instance addressing (for block-select) */
#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4

#define  XCVR_CNTL_ADDR  0x0

/* ---- Reg addressing (within block) */
#define XCVR_CNTL_REG_ADDR_BIT_L 2
#define XCVR_CNTL_REG_ADDR_BIT_H 5
#define XCVR_CNTL_REG_ADDR_WIDTH 4


/* ================================================================
 * ---- Register XC_XCVR_CNTL_REVISION */
#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET    0x000
#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_RESET */
#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET    0x004
#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_STATUS */
#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET    0x008
#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_CNTL */
#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET    0x01c
#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_BRD_INFO */
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET    0x020
#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET    0x024
#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_INTERRUPT */
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET    0x00c
#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET    0x010
#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_SCRATCH */
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET    0x014
#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB      0

/* ================================================================
 * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET    0x018
#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK    0x000
#endif
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK    0xffffffff
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB     31
#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB      0

/* ================================================================
 * Field info for register XC_XCVR_CNTL_REVISION */
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK    0x0000ff00
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT    8
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB    15
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB    8
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK    0x000000ff
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT    0
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB    7
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB    0
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT    0x00000000

/* ================================================================
 * Field info for register XC_XCVR_CNTL_RESET */
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK    0x00020000
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT    17
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB    17
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB    17
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK    0x00010000
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT    16
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB    16
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB    16
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK    0x00008000
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT    15
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB    15
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB    15
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK    0x00004000
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT    14
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB    14
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB    14
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK    0x00002000
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT    13
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB    13
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB    13
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK    0x00001000
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT    12
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB    12
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB    12
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT    0x00000000
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK    0x00000800
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT    11
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB    11
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB    11
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT    0x00000000