📄 hal_ka_sc_auto.h
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/* **************************************************************** * Common defs for reg spec for chip ka_sc * Auto-generated by trex2: DO NOT HAND-EDIT!! * **************************************************************** */#ifndef HAL_KA_SC_AUTO_H#define HAL_KA_SC_AUTO_H/* ---------------------------------------------------------------- * For block: 'scan' *//* ---- Block instance addressing (for block-select) */#define SCAN_BLOCK_ADDR_BIT_L 7#define SCAN_BLOCK_ADDR_BIT_H 9#define SCAN_BLOCK_ADDR_WIDTH 3#define SCAN_ADDR 0x0/* ---- Reg addressing (within block) */#define SCAN_REG_ADDR_BIT_L 2#define SCAN_REG_ADDR_BIT_H 6#define SCAN_REG_ADDR_WIDTH 5/* ================================================================ * ---- Register KA_SC_SCAN_REVISION */#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_RESET */#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_STATUS */#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_CNTL */#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_BRD_INFO */#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_SCAN_FROM_0 */#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_SCAN_FROM_1 */#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_SCAN_TO_0 */#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_SCAN_TO_1 */#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_SCAN_CTRL */#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_PLL_CTRL */#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_DR_CLK_COUNT */#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_BRD_BRD_IN */#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_MISC */#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000#endif#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0/* ================================================================ * ---- Register KA_SC_SCAN_INTERRUPT */#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c⌨️ 快捷键说明
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