timer_preset.xco

ise9.1官方的使用手册中配套用的fpga入门代码

##############################################################
#
# Xilinx Core Generator version IP1_J.12
# Date: Thu Mar 15 16:38:03 2007
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s700a
SET devicefamily = spartan3a
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg484
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=C:/Temp/tutorial/wtut_sc/wtut_sc_completed/definition1_times.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=timer_preset
CSET data_width=20
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qspo=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qspo=false
# END Parameters
GENERATE
# CRC: 5b713561