2410addr.h

arm 2410上的hdlc server 通信程序

//=============================================================================
// File Name : 2410addr.h
// Function  : S3C2410 Define Address Register
// Program   : Shin, On Pil (SOP)
// Date      : May 06, 2002
// Version   : 0.0
// History
//   0.0 : Programming start (February 15,2002) -> SOP
//         INTERRUPT rPRIORITY 0x4a00000a -> 0x4a00000c       (May 02, 2002 SOP)
//         RTC BCD DAY and DATE Register Name Correction      (May 06, 2002 SOP) 
//=============================================================================
/*
#ifndef __2410ADDR_H__
#define __2410ADDR_H__
#ifdef __cplusplus
extern "C" {
#endif
*/
#define U8  unsigned char
#include "option.h"
// Memory control 
#define rBWSCON    (*(volatile unsigned *)0xB0800000) //Bus width & wait status
#define rBANKCON0  (*(volatile unsigned *)0xB0800004) //Boot ROM control
#define rBANKCON1  (*(volatile unsigned *)0xB0800008) //BANK1 control
#define rBANKCON2  (*(volatile unsigned *)0xB080000c) //BANK2 cControl
#define rBANKCON3  (*(volatile unsigned *)0xB0800010) //BANK3 control
#define rBANKCON4  (*(volatile unsigned *)0xB0800014) //BANK4 control
#define rBANKCON5  (*(volatile unsigned *)0xB0800018) //BANK5 control
#define rBANKCON6  (*(volatile unsigned *)0xB080001c) //BANK6 control
#define rBANKCON7  (*(volatile unsigned *)0xB0800020) //BANK7 control
#define rREFRESH   (*(volatile unsigned *)0xB0800024) //DRAM/SDRAM refresh
#define rBANKSIZE  (*(volatile unsigned *)0xB0800028) //Flexible Bank Size
#define rMRSRB6    (*(volatile unsigned *)0xB080002c) //Mode register set for SDRAM
#define rMRSRB7    (*(volatile unsigned *)0xB0800030) //Mode register set for SDRAM


// USB Host


// INTERRUPT
#define rSRCPND     (*(volatile unsigned *)0xB0A00000) //Interrupt request status
#define rINTMOD     (*(volatile unsigned *)0xB0A00004) //Interrupt mode control
#define rINTMSK     (*(volatile unsigned *)0xB0A00008) //Interrupt mask control
#define rPRIORITY   (*(volatile unsigned *)0xB0A0000c) //IRQ priority control
#define rINTPND     (*(volatile unsigned *)0xB0A00010) //Interrupt request status
#define rINTOFFSET  (*(volatile unsigned *)0xB0A00014) //Interruot request source offset
#define rSUBSRCPND  (*(volatile unsigned *)0xB0A00018) //Sub source pending
#define rINTSUBMSK  (*(volatile unsigned *)0xB0A0001c) //Interrupt sub mask


// DMA
#define rDISRC0     (*(volatile unsigned *)0xB0B00000) //DMA 0 Initial source
#define rDISRCC0    (*(volatile unsigned *)0xB0B00004) //DMA 0 Initial source control
#define rDIDST0     (*(volatile unsigned *)0xB0B00008) //DMA 0 Initial Destination
#define rDIDSTC0    (*(volatile unsigned *)0xB0B0000c) //DMA 0 Initial Destination control
#define rDCON0      (*(volatile unsigned *)0xB0B00010) //DMA 0 Control
#define rDSTAT0     (*(volatile unsigned *)0xB0B00014) //DMA 0 Status
#define rDCSRC0     (*(volatile unsigned *)0xB0B00018) //DMA 0 Current source
#define rDCDST0     (*(volatile unsigned *)0xB0B0001c) //DMA 0 Current destination
#define rDMASKTRIG0 (*(volatile unsigned *)0xB0B00020) //DMA 0 Mask trigger

#define rDISRC1     (*(volatile unsigned *)0xB0B00040) //DMA 1 Initial source
#define rDISRCC1    (*(volatile unsigned *)0xB0B00044) //DMA 1 Initial source control
#define rDIDST1     (*(volatile unsigned *)0xB0B00048) //DMA 1 Initial Destination
#define rDIDSTC1    (*(volatile unsigned *)0xB0B0004c) //DMA 1 Initial Destination control
#define rDCON1      (*(volatile unsigned *)0xB0B00050) //DMA 1 Control
#define rDSTAT1     (*(volatile unsigned *)0xB0B00054) //DMA 1 Status
#define rDCSRC1     (*(volatile unsigned *)0xB0B00058) //DMA 1 Current source
#define rDCDST1     (*(volatile unsigned *)0xB0B0005c) //DMA 1 Current destination
#define rDMASKTRIG1 (*(volatile unsigned *)0xB0B00060) //DMA 1 Mask trigger

#define rDISRC2     (*(volatile unsigned *)0xB0B00080) //DMA 2 Initial source
#define rDISRCC2    (*(volatile unsigned *)0xB0B00084) //DMA 2 Initial source control
#define rDIDST2     (*(volatile unsigned *)0xB0B00088) //DMA 2 Initial Destination
#define rDIDSTC2    (*(volatile unsigned *)0xB0B0008c) //DMA 2 Initial Destination control
#define rDCON2      (*(volatile unsigned *)0xB0B00090) //DMA 2 Control
#define rDSTAT2     (*(volatile unsigned *)0xB0B00094) //DMA 2 Status
#define rDCSRC2     (*(volatile unsigned *)0xB0B00098) //DMA 2 Current source
#define rDCDST2     (*(volatile unsigned *)0xB0B0009c) //DMA 2 Current destination
#define rDMASKTRIG2 (*(volatile unsigned *)0xB0B000a0) //DMA 2 Mask trigger

#define rDISRC3     (*(volatile unsigned *)0xB0B000c0) //DMA 3 Initial source
#define rDISRCC3    (*(volatile unsigned *)0xB0B000c4) //DMA 3 Initial source control
#define rDIDST3     (*(volatile unsigned *)0xB0B000c8) //DMA 3 Initial Destination
#define rDIDSTC3    (*(volatile unsigned *)0xB0B000cc) //DMA 3 Initial Destination control
#define rDCON3      (*(volatile unsigned *)0xB0B000d0) //DMA 3 Control
#define rDSTAT3     (*(volatile unsigned *)0xB0B000d4) //DMA 3 Status
#define rDCSRC3     (*(volatile unsigned *)0xB0B000d8) //DMA 3 Current source
#define rDCDST3     (*(volatile unsigned *)0xB0B000dc) //DMA 3 Current destination
#define rDMASKTRIG3 (*(volatile unsigned *)0xB0B000e0) //DMA 3 Mask trigger


// CLOCK & POWER MANAGEMENT
#define rLOCKTIME   (*(volatile unsigned *)0xB0C00000) //PLL lock time counter
#define rMPLLCON    (*(volatile unsigned *)0xB0C00004) //MPLL Control
#define rUPLLCON    (*(volatile unsigned *)0xB0C00008) //UPLL Control
#define rCLKCON     (*(volatile unsigned *)0xB0C0000c) //Clock generator control
#define rCLKSLOW    (*(volatile unsigned *)0xB0C00010) //Slow clock control
#define rCLKDIVN    (*(volatile unsigned *)0xB0C00014) //Clock divider control


// LCD CONTROLLER
#define rLCDCON1    (*(volatile unsigned *)0xB0D00000) //LCD control 1
#define rLCDCON2    (*(volatile unsigned *)0xB0D00004) //LCD control 2
#define rLCDCON3    (*(volatile unsigned *)0xB0D00008) //LCD control 3
#define rLCDCON4    (*(volatile unsigned *)0xB0D0000c) //LCD control 4
#define rLCDCON5    (*(volatile unsigned *)0xB0D00010) //LCD control 5
#define rLCDSADDR1  (*(volatile unsigned *)0xB0D00014) //STN/TFT Frame buffer start address 1
#define rLCDSADDR2  (*(volatile unsigned *)0xB0D00018) //STN/TFT Frame buffer start address 2
#define rLCDSADDR3  (*(volatile unsigned *)0xB0D0001c) //STN/TFT Virtual screen address set
#define rREDLUT     (*(volatile unsigned *)0xB0D0020) //STN Red lookup table
#define rGREENLUT   (*(volatile unsigned *)0xB0D00024) //STN Green lookup table 
#define rBLUELUT    (*(volatile unsigned *)0xB0D00028) //STN Blue lookup table
#define rDITHMODE   (*(volatile unsigned *)0xB0D0004c) //STN Dithering mode
#define rTPAL       (*(volatile unsigned *)0xB0D00050) //TFT Temporary palette
#define rLCDINTPND  (*(volatile unsigned *)0xB0D00054) //LCD Interrupt pending
#define rLCDSRCPND  (*(volatile unsigned *)0xB0D00058) //LCD Interrupt source
#define rLCDINTMSK  (*(volatile unsigned *)0xB0D0005c) //LCD Interrupt mask
#define rLPCSEL     (*(volatile unsigned *)0xB0D00060) //LPC3600 Control
#define PALETTE     0xB0D00400                         //Palette start address


// NAND flash
#define rNFCONF     (*(volatile unsigned *)0xB0E00000)      //NAND Flash configuration
#define rNFCMD      (*(volatile U8 *)0xB0E00004)            //NADD Flash command
#define rNFADDR     (*(volatile U8 *)0xB0E00008)            //NAND Flash address
#define rNFDATA     (*(volatile U8 *)0xB0E0000c)            //NAND Flash data
#define rNFSTAT     (*(volatile unsigned *)0xB0E00010)      //NAND Flash operation status
#define rNFECC      (*(volatile unsigned *)0xB0E00014)      //NAND Flash ECC
#define rNFECC0     (*(volatile U8  *)0xB0E00014)
#define rNFECC1     (*(volatile U8  *)0xB0E00015)
#define rNFECC2     (*(volatile U8  *)0xB0E00016)

// UART
#define rULCON0     (*(volatile unsigned *)0xB1000000) //UART 0 Line control
#define rUCON0      (*(volatile unsigned *)0xB1000004) //UART 0 Control
#define rUFCON0     (*(volatile unsigned *)0xB1000008) //UART 0 FIFO control
#define rUMCON0     (*(volatile unsigned *)0xB100000c) //UART 0 Modem control
#define rUTRSTAT0   (*(volatile unsigned *)0xB1000010) //UART 0 Tx/Rx status
#define rUERSTAT0   (*(volatile unsigned *)0xB1000014) //UART 0 Rx error status
#define rUFSTAT0    (*(volatile unsigned *)0xB1000018) //UART 0 FIFO status
#define rUMSTAT0    (*(volatile unsigned *)0xB100001c) //UART 0 Modem status
#define rUBRDIV0    (*(volatile unsigned *)0xB1000028) //UART 0 Baud rate divisor

#define rULCON1     (*(volatile unsigned *)0xB1004000) //UART 1 Line control
#define rUCON1      (*(volatile unsigned *)0xB1004004) //UART 1 Control
#define rUFCON1     (*(volatile unsigned *)0xB1004008) //UART 1 FIFO control
#define rUMCON1     (*(volatile unsigned *)0xB100400c) //UART 1 Modem control
#define rUTRSTAT1   (*(volatile unsigned *)0xB1004010) //UART 1 Tx/Rx status
#define rUERSTAT1   (*(volatile unsigned *)0xB1004014) //UART 1 Rx error status
#define rUFSTAT1    (*(volatile unsigned *)0xB1004018) //UART 1 FIFO status
#define rUMSTAT1    (*(volatile unsigned *)0xB100401c) //UART 1 Modem status
#define rUBRDIV1    (*(volatile unsigned *)0xB1004028) //UART 1 Baud rate divisor

#define rULCON2     (*(volatile unsigned *)0xB1008000) //UART 2 Line control
#define rUCON2      (*(volatile unsigned *)0xB1008004) //UART 2 Control
#define rUFCON2     (*(volatile unsigned *)0xB1008008) //UART 2 FIFO control
#define rUMCON2     (*(volatile unsigned *)0xB100800c) //UART 2 Modem control
#define rUTRSTAT2   (*(volatile unsigned *)0xB1008010) //UART 2 Tx/Rx status
#define rUERSTAT2   (*(volatile unsigned *)0xB1008014) //UART 2 Rx error status
#define rUFSTAT2    (*(volatile unsigned *)0xB1008018) //UART 2 FIFO status
#define rUMSTAT2    (*(volatile unsigned *)0xB100801c) //UART 2 Modem status
#define rUBRDIV2    (*(volatile unsigned *)0xB1008028) //UART 2 Baud rate divisor

#ifdef __BIG_ENDIAN
#define rUTXH0      (*(volatile unsigned char *)0xB1000023) //UART 0 Transmission Hold
#define rURXH0      (*(volatile unsigned char *)0xB1000027) //UART 0 Receive buffer
#define rUTXH1      (*(volatile unsigned char *)0xB1004023) //UART 1 Transmission Hold
#define rURXH1      (*(volatile unsigned char *)0xB1004027) //UART 1 Receive buffer
#define rUTXH2      (*(volatile unsigned char *)0xB1008023) //UART 2 Transmission Hold
#define rURXH2      (*(volatile unsigned char *)0xB1008027) //UART 2 Receive buffer

#define WrUTXH0(ch) (*(volatile unsigned char *)0xB1000023)=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)0xB1000027)
#define WrUTXH1(ch) (*(volatile unsigned char *)0xB1004023)=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)0xB1004027)
#define WrUTXH2(ch) (*(volatile unsigned char *)0xB1008023)=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)0xB1008027)

#define UTXH0       (0xB1000020+3)  //Byte_access address by DMA
#define URXH0       (0xB1000024+3)
#define UTXH1       (0xB1004020+3)
#define URXH1       (0xB1004024+3)
#define UTXH2       (0xB1008020+3)
#define URXH2       (0xB1008024+3)

#else //Little Endian
#define rUTXH0 (*(volatile unsigned char *)0xB1000020) //UART 0 Transmission Hold
#define rURXH0 (*(volatile unsigned char *)0xB1000024) //UART 0 Receive buffer
#define rUTXH1 (*(volatile unsigned char *)0xB1004020) //UART 1 Transmission Hold
#define rURXH1 (*(volatile unsigned char *)0xB1004024) //UART 1 Receive buffer
#define rUTXH2 (*(volatile unsigned char *)0xB1008020) //UART 2 Transmission Hold
#define rURXH2 (*(volatile unsigned char *)0xB1008024) //UART 2 Receive buffer

#define WrUTXH0(ch) (*(volatile unsigned char *)0xB1000020)=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)0xB1000024)
#define WrUTXH1(ch) (*(volatile unsigned char *)0xB1004020)=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)0xB1004024)
#define WrUTXH2(ch) (*(volatile unsigned char *)0xB1008020)=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)0xB1008024)