dec5502_dma.c

在CCS开发环境下的DSP 5502的DMA配置框架程序

/******************************************************************************/
/*  Copyright 2004 by SEED Electronic Technology LTD.                         */
/*  All rights reserved. SEED Electronic Technology LTD.                      */
/*  Restricted rights to use, duplicate or disclose this code are             */
/*  granted through contract.                                                 */
/*                                                                            */
/*  MODULE NAME... DMA														  */
/*  FILENAME...... DEC5502_DMA.c										  	  */
/*  PROJECT....... Data transifer between DARAM and SDRAM through DMA channel */
/*  DESCRIPTION:  															  */
/*  This is an example for DMA operaton of C5502							  */
/*                                                                            */
/*  作者:艾岩                                                                 */
/*  版本:1.0                                                                  */
/*  日期:06.8.11                                                              */
/******************************************************************************/


#include <stdio.h>
#include <csl.h>
#include <csl_irq.h>
#include <csl_dma.h>
#include <csl_emif.h>
#include <csl_emifBhal.h>

#include <csl_gpt.h>

/* Constant defines transfer length */
#define FrameLength      3000
#define ElementLength	 4
#define DataLength 		 FrameLength*ElementLength

/* Place SrcData and DstData of DMA transfer in seperate memory section	 */
/* to better control placement in user specified memory range  			 */
#pragma DATA_SECTION(SrcData,"SrcDataMem")
Uint16 SrcData[DataLength];
    
#pragma DATA_SECTION(DstData, "DstDataMem")
Uint16 DstData[DataLength];

/* Define macro to access Timer 0 memory-mapped count registers */
#define MYGPTCINT1_0 (*(volatile ioport Uint16*)(0x1008))
#define MYGPTCINT2_0 (*(volatile ioport Uint16*)(0x1009))
#define MYGPTCINT3_0 (*(volatile ioport Uint16*)(0x100A))
#define MYGPTCINT4_0 (*(volatile ioport Uint16*)(0x100B))

/* This example effects a single-frame transfer of 3600     */
/* elements from SDRAM to DARAM, via DMA                    */
/* The macro invocation reflect the settings required in    */
/* DMA control registers to make this happen.               */                             
/*   DMACSDP       dstben    == 2                           */
/*                 dstpack   == 1                           */
/*                 dst       == 0                           */
/*                 srcben    == 2                           */
/*                 srcpack   == 1                           */
/*                 src       == 2                           */
/*                 datatype  == 2                           */
/*                                                          */
/*   DMACCR        dstamode  == 1                           */
/*                 srcamode  == 1                           */
/*                 endprog   == 0                           */
/*                 repeat    == 0                           */
/*                 autoinit  == 0                           */
/*                 en        == 0                           */
/*                 prio      == 0                           */
/*                 fs        == 0                           */
/*                 sync      == 0                           */
/*                                                          */
/*  DMACICR        blockie   == 1                           */
/*                 lastie    == 1                           */
/*                 frameie   == 1                           */
/*                 firsthalfie == 1                         */
/*                 dropie    == 1                           */
/*                 timeoutie == 1                           */

DMA_Config  MyConfig = { 
  DMA_DMACSDP_RMK(
    DMA_DMACSDP_DSTBEN_BURST4,				//Destination burst
    //DMA_DMACSDP_DSTBEN_NOBURST,           //Destination NO-burst
    DMA_DMACSDP_DSTPACK_ON,					//Destination data package
    //DMA_DMACSDP_DSTPACK_OFF,              //Destination NO-data package
    DMA_DMACSDP_DST_DARAM,			        //Destination selection DARAM
    DMA_DMACSDP_SRCBEN_BURST4,				//Source burst
    //DMA_DMACSDP_SRCBEN_NOBURST,           //Source NO-burst
    DMA_DMACSDP_SRCPACK_ON,					//Source data package 
    //DMA_DMACSDP_SRCPACK_OFF,              //Source NO-data package
    DMA_DMACSDP_SRC_EMIF,					//Source selection SDRAM
    DMA_DMACSDP_DATATYPE_32BIT				/* 32bits 	*/
  ),                                    	/* DMACSDP 	*/
  DMA_DMACCR_RMK(
    DMA_DMACCR_DSTAMODE_POSTINC,            //Destination address mode
    DMA_DMACCR_SRCAMODE_POSTINC,            //Source address mode
    DMA_DMACCR_ENDPROG_OFF,                 //End of programmation bit
    DMA_DMACCR_REPEAT_OFF,                  //Repeat condition
    DMA_DMACCR_AUTOINIT_OFF,                //Auto initialization bit
    DMA_DMACCR_EN_STOP,                     //Channel enable
    DMA_DMACCR_PRIO_HI,                     //Channel priority
    DMA_DMACCR_FS_ENABLE,                   
    DMA_DMACCR_SYNC_NONE                    //Synchronization control
  ),                                       	/* DMACCR   */
  DMA_DMACICR_RMK(
    DMA_DMACICR_BLOCKIE_OFF,
    DMA_DMACICR_LASTIE_OFF,
    DMA_DMACICR_FRAMEIE_ON,                 //Whole frame interrupt enable
    DMA_DMACICR_FIRSTHALFIE_OFF,
    DMA_DMACICR_DROPIE_OFF,
    DMA_DMACICR_TIMEOUTIE_OFF
  ),                                       	/* DMACICR  */
    (DMA_AdrPtr) &SrcData,              	/* DMACSSAL */
    0,                         				/* DMACSSAU */
    (DMA_AdrPtr) &DstData,              	/* DMACDSAL */
    0,                         				/* DMACDSAU */
    FrameLength,                            /* DMACEN   */
    ElementLength,                          /* DMACFN   */
    0,                                     	/* DMACFI   */
    0,                                     	/* DMACEI   */
    0,								/* DMA Channel Destination Frame Index Register */
    0     							/* DMA Channel Destination Element Index */
};


/* Define and initialize the GPT module configuration structure  */
GPT_Config  MyGptConfig = {
0, 									//Emulation management register
0,		 							//GPIO interrupt control register
0,	 								//GPIO enable register
0,		 							//GPIO direction register
0,		 							//GPIO data register
0xFFFF, 							//Timer period register 1
0xFFFF,	 							//Timer period register 2
0xFFFF,								//Timer period register 3
0xFFFF, 							//Timer period register 4
GPT_GPTCTL1_RMK(					//Timer control register 1
  GPT_GPTCTL1_TIEN_NOT_GATED,
  GPT_GPTCTL1_CLKSRC_VBUS,
  GPT_GPTCTL1_ENAMODE_ONCE,			//The timer is enabled one time
  GPT_GPTCTL1_PWID_INACTIVE_1CYCLE,
  GPT_GPTCTL1_CP_CLOCK_MODE,
  GPT_GPTCTL1_INVIN_DONT_INVERT_OUTPUT,
  GPT_GPTCTL1_INVOUT_DONT_INVERT_OUTPUT
  ), 			
GPT_GPTCTL2_RMK(					//Timer control register 2
  GPT_GPTCTL2_TIEN_NOT_GATED,
  GPT_GPTCTL2_CLKSRC_VBUS,
  GPT_GPTCTL2_ENAMODE_CONTINUOUS,
  GPT_GPTCTL2_PWID_INACTIVE_1CYCLE,
  GPT_GPTCTL2_CP_CLOCK_MODE,
  GPT_GPTCTL2_INVIN_DONT_INVERT_OUTPUT,
  GPT_GPTCTL2_INVOUT_DONT_INVERT_OUTPUT
  ), 			
GPT_GPTGCTL1_RMK(					//Global timer control register
  GPT_GPTGCTL1_PSC34_DEFAULT,
  GPT_GPTGCTL1_TIMMODE_64BIT_GPTIM,	//The timer is in the 64-bit general-purpose timer mode
  GPT_GPTGCTL1_TIM34RS_NOT_IN_RESET,
  GPT_GPTGCTL1_TIM12RS_NOT_IN_RESET
  ) 	
};

/* Create a TIMER_Handle object for use with TIMER_open */
GPT_Handle 	 hGpt;

/* Function prototypes */
void TaskFxn(void);

/* Define a DMA_Handle object */
DMA_Handle MyDmaH;
Uint16 i, j;   
Uint16 Errcount = 0;

/* Define three int variables to get the values of GP timer 0 */
Uint16 cnt1 = 0;
Uint16 cnt2 = 0;
Uint16 cnt3 = 0;
Uint16 cnt4 = 0;

/********************************************************************/
/* NOTE:															*/
/*------------------------------------------------------------------*/
/* 	Because software reset have no effect on count registers,   	*/	
/* 	So in order to get the correct time value of DMA transifer, 	*/
/* 	We should take following steps for next time run: 				*/
/* 		First:  Reset CPU through Debug ->Reset CPU operation     	*/
/* 		Second: Click Debug->Restart								*/
/* 		Third:  Click Debug->Go Main 								*/
/* 		Finally: Press the RUN graphic button to run program		*/
/*------------------------------------------------------------------*/
/* 	When source and destination ports all take burst and data 		*/
/*  package mode , The process of DMA transifer will take about		*/
/*  5.3 ms. If source and destination  ports are taken NO-burst		*/
/*  and No-data package mode, it will take about 4.7ms(if main 		*/
/*  frequency is 300MHz, take about 3.42ms) 						*/
/********************************************************************/

void main(void)
{
    /* Initialize CSL library - This is REQUIRED!!! */
    CSL_init();
    
    /* 设置系统的运行速度为300MHz */
    PLL_setFreq(1, 0xF, 0, 1, 3, 3, 0);
    
    /* EMIF为全EMIF接口 */
    CHIP_RSET(XBSR,0x0001);
    
    /* 初始化DSP的外部SDRAM */
    Emif_Config();
    
    /* Open Timer 0, set registers to power on defaults */
	/* And return handle of Timer 0 */
	hGpt = GPT_open(GPT_DEV0, GPT_OPEN_RESET);
   
    /* Write configuration structure values to Timer 0 control regs */ 
	GPT_config(hGpt, &MyGptConfig); 

    /* Initialize source and destination buffers    */
    for (i = 0; i <= (DataLength - 1); i++)
    {
        DstData[i] = 0;
        SrcData[i] = i + 1;
    }

    /* Call Function For DMA Transfer */
    TaskFxn();
    	
}

void TaskFxn(void)
{
    /* Open DMA Channel 0 */
    MyDmaH = DMA_open(DMA_CHA0, 0);    

    /* By default, the TMS320C55xx compiler assigns all data symbols word */
    /* addresses. The DMA however, expects all addresses to be byte       */
    /* addresses. Therefore, we must shift the address by 2 in order to   */
    /* change the word address to a byte address forthe DMA transfer.     */   
    MyConfig.dmacssal = (DMA_AdrPtr)(((Uint32)(MyConfig.dmacssal)<<1)&0xFFFF);
    MyConfig.dmacdsal = (DMA_AdrPtr)(((Uint32)(MyConfig.dmacdsal)<<1)&0xFFFF);

	MyConfig.dmacssau = (((Uint32) &SrcData) >> 15) & 0xFFFF;
	MyConfig.dmacdsau = (((Uint32) &DstData) >> 15) & 0xFFFF;
	
    /* Write configuration structure values to DMA control registers */
    DMA_config(MyDmaH, &MyConfig);                   

	/* Start Timer 0 */
	GPT_start(hGpt);//此行设置断点

    /* Enable DMA channel to begin transfer */
    DMA_start(MyDmaH);
	
    /* Wait for FRAME status bit in DMA status register to signal */
    /* transfer is complete.                                      */
    while (!DMA_FGETH(MyDmaH,DMACSR,FRAME)) 
    {
    	/* Wait for FRAME status bit to set to indicate frame transifer is completed */
    }
	
	/* Stop Timer */
	GPT_stop(hGpt);
	
	/* Get the values of timer count registers */
	cnt1 = MYGPTCINT1_0;//此行设置断点
	cnt2 = MYGPTCINT2_0;
	cnt3 = MYGPTCINT3_0;
	cnt4 = MYGPTCINT4_0;
	
    /* Check data values to make sure transfer happened correctly */
    
    for (i = 0; i <= (DataLength - 1); i++) 
    {
        if (DstData[i] != SrcData[i]) 
        {
            ++Errcount;
        }
    }
            
    if (Errcount) 
    {
        printf("SEED_DEC5502 DMA 操作失败\n");
    }
    else 
    {
        printf("SEED_DEC5502 DMA 操作成功\n");
    }
 
    /* We are through with DMA, so close it */
    DMA_close(MyDmaH); 
}

/******************************************************************************\
* End of DEC5502_DMA.c
\******************************************************************************/