excalib.s

vxworks source code, used for develop vxworks system.

	bf	excUnlock	/* virtual interrupt vector table.   */

	mov.l	@(12,r5),r3	/* r3: TRA 0x000, 0x004, ... 0x3fc */
	mov	r3,r4
	mov	#3,r1
	shld	r1,r4		/* r4: 0x000, 0x020, ... 0x1fe0 */

excUnlock:
	tst	r2,r2			/* continue locking if intPrioTable */
	bt	excChkBusErr		/* entry is null, otherwise         */
	ldc	r2,sr			/* UNLOCK INTERRUPTS                */

excChkBusErr:
	mov.l	ExcBErrVecNum,r1;
	mov.l	@r1,r0;			/* r0: 0, 1, 2, ... 255 */
	shll2	r0			/* If this is a bus error interrupt,*/
	cmp/eq	r3,r0			/* force to call excExcHandle since */
	bt	excSetDefault		/* the vector entry is excBErrStub. */

	mov.w	ExcVecTblOffset,r1
	stc	vbr,r0
	add	r1,r0
	bra	excDispatch;
	mov.l	@(r0,r3),r2

excSetDefault:
	mov.l	ExcExcHandle,r2

excDispatch:
	mov	#-5,r1
	shld	r1,r4		/* r4: 0, 1, 2, ... 255 */
	jsr	@r2;		/* excExcHandle (INUM, ESFSH, REG_SET) */
	mov	sp,r6		/*                r4    r5      r6     */

	/* only vxMemProbeTrap/fppProbeTrap come here */

	add	#8,sp			/* skip vbr/gbr */
	lds.l	@sp+,pr
	mov.l	@sp+,r0
	mov.l	@sp+,r1
	mov.l	@sp+,r2
	mov.l	@sp+,r3			/* LOCK INTERRUPTS, RB=0 */
	mov.l	@sp+,r4;		mov.l	IntLockSR,r7
	mov.l	@sp+,r5;		mov.l	@r7,r7
	mov.l	@sp+,r6;		ldc	r7,sr
	mov.l	@sp+,r7
	lds.l	@sp+,mach
	lds.l	@sp+,macl
	add	#32,sp			/* skip r8-r15 */

	ldc.l	@sp+,r7_bank		/* r7_bank1 = spc */
	ldc.l	@sp+,r6_bank		/* r6_bank1 = ssr */
	ldc	r5,  r5_bank		/* r5_bank1 = r5  */

	mov.l	IntBlockSR,r5
	mov.l	@r5,r5
	ldc	r5,sr			/* BLOCK EXCEPTION/INTERRUPTS, RB=1 */

	ldc	r5,r5_bank		/* r5_bank0 = r5  */
	ldc	r6,ssr
	ldc	r7,spc
	rte;				/* UNBLOCK INTERRUPTS/EXCEPTION */
	add	#8,sp			/* skip EXPEVT, TRA/TEA */

			.align	2
#if (CPU==SH7750)
EFF000000:		.long	0xff000000
#endif
XCFFFFFFF:		.long	0xcfffffff
IntBlockSR:		.long	_intBlockSR			/* intArchLib */
IntLockSR:		.long	_intLockTaskSR			/* intArchLib */
ExcExcHandle:		.long	_excExcHandle			/* excArchLib */
ExcBErrVecNum:		.long	_excBErrVecNum			/* excArchLib */
EvtFpu:			.word	0x120
EvtTrapa:		.word	0x160
MMU_STUB_OFFSET:	.word	SH7700_TLB_STUB_OFFSET		/* ivSh.h */
ExcVecTblOffset:	.word	SH7700_VEC_TABLE_OFFSET		/* ivSh.h */
IntPrioTableOffset:	.word	SH7700_INT_PRIO_TABLE_OFFSET	/* ivSh.h */
excStubEnd:
			.align	2
			.type	_excStubSize,@object
			.size	_excStubSize,4
_excStubSize:		.long	excStubEnd - _excStub

/******************************************************************************
*
* excBErrStub - bus timeout error interrupt handling stub (SH7750/SH7700)
*
* This stub code is attached to a virtual interrupt vector table entry
* by excVecInit(), to a slot specified by excBErrVecNum.  Thus this code
* is dispatched from intStub, with INTEVT/ssr/spc on interrupt stack.
* The object here is to fake the bus error interrupt as an exception:
* (1) push the INTEVT code to EXPEVT register, (2) return to task's stack
* if not nested, (3) then branch to excStub, the generic exception handling
* stub.
*
* NOMANUAL
*
*	   [ task's stack ]               [ interrupt stack ]
*				
*	|  aaa	|     vxIntStackBase ->	+-------+	|	|
*	|__bbb__|<----------------------|task'sp|	|_______| +12
*	|	|			|INTEVT	|	|INTEVT	|  +8
*					|  ssr	|	|  ssr	|  +4
*				  sp ->	|__spc__|	|__spc__|  +0
*					|	|	|	|
*/
	.align	_ALIGN_COPY_TEXT
	.type	_excBErrStub,@function

_excBErrStub:				/* MD=1, RB=1, BL=1 */
	mov.l	@(8,sp),r0;
#if	(CPU==SH7750)
	mov.l	BE_FF000000,r1
	mov.l	r0,@(EXPEVT,r1)		/* INTEVT -> EXPEVT */
#else
	mov	#EXPEVT,r1
	mov.l	r0,@r1			/* INTEVT -> EXPEVT */
#endif
	stc	vbr,r1;
	mov.l	@(SH7700_ARE_WE_NESTED_OFFSET,r1),r0
	rotr	r0
	mov.l	r0,@(SH7700_ARE_WE_NESTED_OFFSET,r1) /* update areWeNested */
	bf.s	excBErrNested
	add	#12,sp			/* skip spc/ssr/INTEVT */

	mov.l	@sp,sp			/* return to task's stack */
excBErrNested:
	mov.w	BE_ExcStubOffset,r0
	stc	vbr,r1
	add	r1,r0
	jmp	@r0;			/* jump to _excStub in P1/P2 */
	nop

			.align	2
#if (CPU==SH7750)
BE_FF000000:		.long	0xff000000
#endif
BE_ExcStubOffset:	.word	SH7700_EXC_STUB_OFFSET
excBErrStubEnd:
			.align	2
			.type	_excBErrStubSize,@object
			.size	_excBErrStubSize,4
_excBErrStubSize:	.long	excBErrStubEnd - _excBErrStub

/******************************************************************************
*
* excIntStub - uninitialized interrupt handler (SH7750/SH7700)
*
* This routine is dispatched from intStub, with INTEVT/ssr/spc on interrupt
* stack.  It forms a REG_SET structure on stack, then calls the generic
* uninitialized interrupt handler (excIntHandle()).  Then it reforms the
* stack frame and jumps to intExit.
*
* NOMANUAL
*
*   [task's stack]  [interrupt stack]         <before intExit>
*
*	|  aaa	|     	+-------+		|	|
*	|__bbb__|<------|task'sp| +68		|_______|
*	|	|	|INTEVT	| +64	+104	|INTEVT	|
*			|  ssr	| +60	+100	|  ssr	|
*	r5 ------ sp ->	|_ spc _| +56	+96	|  spc	|
*		-4	|  ssr	| +52	+92	|  pr	|
*		-8	|  spc	| +48	+88	|  r0	|
*		-12	|  r15	| +44	+84	|  r1	|
*			|  r14	| +40	+80	|  r2	|
*			|  r13	| +36	+76	|  r3	|
*			|  r12	| +32	+72	|  r4	|
*			|  r11	| +28	+68	|  r5	|
*			|  r10	| +24	+64	|  r6	|
*			|  r9	| +20	+60	|  r7	|
*			|  r8	| +16	+56	| mach	|
*			| macl	| +12	+52	| macl	|
*		  	| mach	| +8	+48	|	|
*			|  r7	| +4	+44
*			|  r6	| +0	+40
*		 	|  r5	|	+36
*		  sp ->	|  r4	|	+32
*			|  r3	|	+28
*			|  r2	|	+24
*			|  r1	|	+20
*			|  r0	|	+16
*			|  pr	|	+12
*			|  gbr	|	+8
*		REG_SET	|_ vbr _|	+4
*			| errno	|	+0
*			|	|	
*/
	.align	_ALIGN_TEXT
	.type	_excIntStub,@function
					/* MD=1, RB=0, BL=0 */
_excIntStub:
	add	#-12,sp
	mov.l	r14, @-sp;				/* save r14       */
	mov.l	r13, @-sp;	mov.l	r12, @-sp	/* save r13/r12   */
	mov.l	r11, @-sp;	mov.l	r10, @-sp	/* save r11/r10   */
	mov.l	r9,  @-sp;	mov.l	r8,  @-sp	/* save r9/r8     */
	sts.l	macl,@-sp;	sts.l	mach,@-sp	/* save macl/mach */
	mov.l	r7,  @-sp;	mov.l	r6,  @-sp	/* save r7/r6     */

	mov.l	@(60,sp),r7;	mov.l	r7,@(52,sp)	/* save ssr */
	mov.l	@(56,sp),r7;	mov.l	r7,@(48,sp)	/* save spc */

	stc	vbr,r6;
	mov	sp,r7
	mov.l	@(SH7700_ARE_WE_NESTED_OFFSET,r6),r6;
	rotr	r6
	bf.s	excIntNested
	add	#68,r7
	mov.l	@r7,r7	/* task's sp */
excIntNested:			mov.l	r7,@(44,sp)	/* save as r15 */

	mov.l	IS_IntCnt,r7
	mov.l	@r7, r6
	add	#1,  r6
	mov.l	r6,  @r7

	mov.l	r5,  @-sp;	mov.l	r4,  @-sp	/* save r5/r6   */
	mov.l	r3,  @-sp;	mov.l	r2,  @-sp	/* save r3/r2   */
	mov.l	r1,  @-sp;	mov.l	r0,  @-sp	/* save r1/r0   */
	sts.l	pr,  @-sp				/* save pr      */
	stc.l	gbr, @-sp;	stc.l	vbr, @-sp	/* save gbr/vbr */
	mov.l	IS_Errno,r7
	mov.l	@r7,  r6;	mov.l	r6,  @-sp	/* save errno   */

	mov	sp,r4
	add	#104,r4
	mov.l	@r4,r4			/* r4: INTEVT */
	mov	#-5,r1
	shld	r1,r4			/* r4: (INTEVT >> 5) */
	mov	sp,r5
	add	#96,r5			/* r5: pEsf */
	mov.l	IS_ExcIntHandle,r0;
	mov	sp,r6
	jsr	@r0;			/* excIntHandle (INUM, pEsf, pRegs) */
	add	#4,r6			/*                r4     r5    r6   */

	mov	sp,r7
	add	#96,r7					/* r7: pEsf */
	mov.l	@(12,sp),r6;	mov.l	r6,@-r7		/* push pr */
	mov.l	@(16,sp),r6;	mov.l	r6,@-r7		/* push r0 */
	mov.l	@(20,sp),r6;	mov.l	r6,@-r7		/* push r1 */
	mov.l	@(24,sp),r6;	mov.l	r6,@-r7		/* push r2 */
	mov.l	@(28,sp),r6;	mov.l	r6,@-r7		/* push r3 */
	mov.l	@(32,sp),r6;	mov.l	r6,@-r7		/* push r4 */
	mov.l	@(36,sp),r6;	mov.l	r6,@-r7		/* push r5 */
	mov.l	@(40,sp),r6;	mov.l	r6,@-r7		/* push r6 */
	mov.l	@(44,sp),r6;	mov.l	r6,@-r7		/* push r7 */
	mov.l	@(48,sp),r6;	mov.l	r6,@-r7		/* push mach */
	mov.l	@(52,sp),r6;	mov.l	r6,@-r7		/* push macl */

	mov.l	IS_IntExit,r0
	mov.l	@sp,r1			/* r1: errno (for intExit) */
	jmp	@r0;			/* exit the ISR thru the kernel */
	mov	r7,sp			/* sp -> macl */

			.align	2
IS_IntCnt:		.long	_intCnt
IS_Errno:		.long	_errno
IS_ExcIntHandle:	.long	_excIntHandle
IS_IntExit:		.long	_intExit


/******************************************************************************
*
* mmuStub - TLB mishit exception handler (SH7750/SH7700)
*
* This is the TLB (Translation Lookaside Buffer) mishit exception handler that
* is pointed by the SH77XX TLB mishit exception vector.  The object here is to
* find a new page table entry from address translation table and load it to
* TLB.  If a valid entry is not found, put EXPEVT in r0 and jump to excTLBfixed.
*
* These instructions are copied to (vbr + 0x400), the SH77XX TLB mishit excep-
* tion vector by the startup routine excVecInit().  As this handler does not
* unblock exception, another TLB mishit exception is fatal and it leads to
* an immediate CPU reset.  To avoid this, the code text is safely placed on
* physical space by proper VBR setup, and the address translation table is also
* built on plysical space by mmuSh7700Lib.  This handler uses R0..R3 in bank-1
* as work registers, thus these four registers are volatile while SR.BL=0.
*
* NOMANUAL
*/

#define PTEH	0x0		/* Page Table Entry High  */
#define PTEL	0x4		/* Page Table Entry Low   */
#define TTB	0x8		/* Translation Table Base */
#define MMUCR	0x10		/* MMU Control Register */

	.align	_ALIGN_COPY_TEXT
	.type	_mmuStub,@function

_mmuStub:			/* MD=1, RB=1, BL=1, IM=? */
#if	(CPU==SH7750)
	mov.l	MS_XFF000000,r3;/* r3: 0xff000000 */
#else	/*CPU==SH7700*/
	mov	#0xf0,r3	/* r3: 0xfffffff0 */
#endif	/*CPU==SH7700*/
	mov	#-10,r0
	mov.l	@(PTEH,r3),r1;	/* r1: ABCDEFGHIJKLMNOPQRSTUV00???????? */
	shld	r0,r1		/* r1: 0000000000ABCDEFGHIJKLMNOPQRSTUV */
	mov.w	MS_X0FFC,r2;	/* r2: 00000000000000000000111111111100 */
	mov	#-12,r0
	and	r1,r2		/* r2: 00000000000000000000KLMNOPQRST00 */
	shld	r0,r1		/* r1: 0000000000000000000000ABCDEFGHIJ */
	mov.l	@(TTB,r3),r0;
	shll2	r1		/* r1: 00000000000000000000ABCDEFGHIJ00 */
	mov.l	@(r0,r1),r0;	/* r0: --> PTELs table */
	cmp/eq	#-1,r0
	bt	mmuStubErr

	mov.l	@(r0,r2),r1;	/* r1: PTEL entry to load */
	swap.b	r1,r0
	tst	#0x01,r0	/* entry invalid if PTEL.V (bit8) is zero */
	bt	mmuStubErr

	mov.l	r1,@(PTEL,r3)	/* update PTEL */
	ldtlb			/* load PTEH/PTEL to TLB */
	nop
	rte;			/* UNBLOCK EXCEPTION */
	nop
		.align	2
#if (CPU==SH7750)
MS_XFF000000:	.long	0xff000000
#endif
MS_X0FFC:	.word	0x0ffc

mmuStubErr:	/* failed to find a valid PTEL entry */
	mov.l	MS_ExcNonTrapaOffset,r0; 
	stc	vbr,r1
	add	r1,r0
#if	(CPU==SH7750)
	jmp	@r0;
	mov.l	@(EXPEVT,r3),r5
#else	/*CPU==SH7700*/
	mov	#EXPEVT,r1
	jmp	@r0;
	mov.l	@r1,r5
#endif	/*CPU==SH7700*/
			.align	2
MS_ExcNonTrapaOffset:	.long	excNonTrapa - _excStub + SH7700_EXC_STUB_OFFSET
mmuStubEnd:
			.type	_mmuStubSize,@object
			.size	_mmuStubSize,4
_mmuStubSize:		.long	mmuStubEnd - _mmuStub

#if (CPU==SH7750)
/******************************************************************************
*
* mmuPciStub - TLB mishit exception handler with virtual PCI space support