fppalib.s

vxworks source code, used for develop vxworks system.

	movt	r0		/* 1: fpscr.sz == 0,  0: fpscr.sz == 1 */

	cmp/eq	r0,r6
	bt	fppRegGetOp
	fschg			/* flip fpscr.sz if necessary */
fppRegGetOp:
	shll2	r4
	braf	r4;
	xor	r0,r0		/* set return value to OK */

	bra	fppRegGetRtn;	fmov	fr0,@r5
	bra	fppRegGetRtn;	fmov	fr1,@r5
	bra	fppRegGetRtn;	fmov	fr2,@r5
	bra	fppRegGetRtn;	fmov	fr3,@r5
	bra	fppRegGetRtn;	fmov	fr4,@r5
	bra	fppRegGetRtn;	fmov	fr5,@r5
	bra	fppRegGetRtn;	fmov	fr6,@r5
	bra	fppRegGetRtn;	fmov	fr7,@r5
	bra	fppRegGetRtn;	fmov	fr8,@r5
	bra	fppRegGetRtn;	fmov	fr9,@r5
	bra	fppRegGetRtn;	fmov	fr10,@r5
	bra	fppRegGetRtn;	fmov	fr11,@r5
	bra	fppRegGetRtn;	fmov	fr12,@r5
	bra	fppRegGetRtn;	fmov	fr13,@r5
	bra	fppRegGetRtn;	fmov	fr14,@r5
	bra	fppRegGetRtn;	fmov	fr15,@r5
fppRegGetRtn:
	rts;
	lds	r3,fpscr	/* restore fpscr */

/******************************************************************************
*
* fppRegSet - set the value of fpu register
*
* STATUS fppRegSet (int regnum, UINT32 *p, int sz)
*
* RETURNS: OK if successful, ERROR otherwise.
*
* NOMANUAL
*/ 
	.align	_ALIGN_TEXT
	.type	_fppRegSet,@function

_fppRegSet:
	sts	fpscr,r3	/* save original fpscr */

	tst	r6,r6
	movt	r6		/* 1: args.sz == 0,  0: args.sz == 1 */
	bt.s	fppRegSetChkAlign
	mov	#0x3,r0		/* fmov.s @r5,FRm requires 4-bytes align */

	mov	#0x7,r0		/* fmov   @r5,DRm requires 8-bytes align */
fppRegSetChkAlign:
	tst	r5,r0		/* check destination address alignment */
	bf.s	fppRegSetRtn;
	mov	#-1,r0		/* set return value to ERROR */

fppRegSetChkSz:
	mov.l	FPSCR_SZ,r2;	/* check current fpscr.sz */
	tst	r3,r2
	movt	r0		/* 1: fpscr.sz == 0,  0: fpscr.sz == 1 */

	cmp/eq	r0,r6
	bt	fppRegSetOp
	fschg			/* invert fpscr.sz */
fppRegSetOp:
	shll2	r4
	braf	r4;
	xor	r0,r0		/* set return value to OK */

	bra	fppRegSetRtn;	fmov	@r5,fr0
	bra	fppRegSetRtn;	fmov	@r5,fr1
	bra	fppRegSetRtn;	fmov	@r5,fr2
	bra	fppRegSetRtn;	fmov	@r5,fr3
	bra	fppRegSetRtn;	fmov	@r5,fr4
	bra	fppRegSetRtn;	fmov	@r5,fr5
	bra	fppRegSetRtn;	fmov	@r5,fr6
	bra	fppRegSetRtn;	fmov	@r5,fr7
	bra	fppRegSetRtn;	fmov	@r5,fr8
	bra	fppRegSetRtn;	fmov	@r5,fr9
	bra	fppRegSetRtn;	fmov	@r5,fr10
	bra	fppRegSetRtn;	fmov	@r5,fr11
	bra	fppRegSetRtn;	fmov	@r5,fr12
	bra	fppRegSetRtn;	fmov	@r5,fr13
	bra	fppRegSetRtn;	fmov	@r5,fr14
	bra	fppRegSetRtn;	fmov	@r5,fr15
fppRegSetRtn:
	rts;
	lds	r3,fpscr	/* restore fpscr */

		.align	2
FPSCR_SZ:	.long	FPSCR_FMOV_32BIT_PAIR
#endif /* CPU==SH7750 */

#ifdef	_WRS_HW_FP_SUPPORT
/******************************************************************************
*
* fppFpulGet - get the value of the fpul register
*
* RETURNS: the value of the fpul register
*
* SEE ALSO: fppFpulSet(), SH Programing Manual and SH Hardware Manual
*
* int fppFpulGet (void)
*/ 
	.align	_ALIGN_TEXT
	.type	_fppFpulGet,@function
	.type	_fpulGet,@function

_fppFpulGet:
_fpulGet:
	rts;
	sts	fpul,r0

/******************************************************************************
*
* fppFpulSet - set the value of the fpul register
*
* RETURNS: N/A
*
* SEE ALSO: fppFpulGet(), SH Programing Manual and SH Hardware Manual
*
* void fppFpulSet
*    (
*    int	value
*    )
*
*/ 
	.align	2
	.type	_fppFpulSet,@function
	.type	_fpulSet,@function

_fppFpulSet:
_fpulSet:
	rts;
	lds	r4,fpul

/******************************************************************************
*
* fppFpscrGet - get the value of the fpscr register
*
* The fpscr register controls which exceptions can be generated
* by the coprocessor. By default no exceptions can be generated.
* This routine can be used to check value of fpscr register.
*
* RETURNS: the value of the fpscr register
*
* SEE ALSO: fppFpscrSet(), SH Programing Manual and SH Hardware Manual
*
* int fppFpscrGet (void)
*
*/ 
	.align	2
	.type	_fppFpscrGet,@function
	.type	_fpscrGet,@function

_fppFpscrGet:
_fpscrGet:
	rts;
	sts	fpscr,r0

/******************************************************************************
*
* fppFpscrSet - set the value of the fpscr register
*
* The fpscr register controls which exceptions can be generated
* by the coprocessor. By default no exceptions can be generated.
* This routine can be used to enable some or all floating point
* excpetions.
*
* RETURNS: N/A
*
* SEE ALSO: fppFpulGet(), SH Programing Manual and SH Hardware Manual
*
* void fppFpscrSet
*    (
*    int	value
*    )
*/ 
	.align	2
	.type	_fppFpscrSet,@function
	.type	_fpscrSet,@function

_fppFpscrSet:
_fpscrSet:
	rts;
	lds	r4,fpscr

/*******************************************************************************
*
* fppProbeSup - fppProbe support routine
*
* This routine executes some coprocessor instruction which will cause a
* bus error if a coprocessor is not present.  A handler, viz. fppProbeTrap,
* should be installed at that vector.  If the coprocessor is present this
* routine returns OK.
*
* SEE ALSO: SH User's Manual
*
* NOMANUAL

* STATUS fppProbeSup ()
*/
	.align	2
	.type	_fppProbeSup,@function

_fppProbeSup:
	mov	#0,r0			/* set return value as OK */
	fabs	fr12			/* exception or nothing */
					/* 0xfc5d is illegal for DSP */
	rts;
	nop

/****************************************************************************
*
* fppProbeTrap - fppProbe support routine
*
* This entry point is momentarily attached to the coprocessor illegal opcode
* error exception vector.  Usually it simply sets r0 to ERROR to indicate that
* the illegal opcode error did occur, and returns from the interrupt.
*
* NOTE: The illegal opcode exception will be handled with 0x400000f0 in SR,
*       hence this routine does not have to be in P1/P2.
*
* NOMANUAL
*
*               |_____________|     +60       __________
*               |TRA/TEA/FPSCR| 96  +56  +12         ^
*               |   EXPEVT    | 92  +52  +8   _____  | ESFSH
*               |     ssr     | 88  +48  +4     ^    |
*       r5 ---> |     spc     | 84  +44  +0     | ___v__
*               |     r15     | 80  +40         |
*               |     r14     | 76  +36         |
*               |     r13     | 72  +32         |
*               |     r12     | 68  +28         |
*               |     r11     | 64  +24         |
*               |     r10     | 60  +20         |
*               |     r9      | 56  +16         |
*               |     r8      | 52  +12         |
*               |    macl     | 48  +8          |
*               |    mach     | 44  +4     REG_SET
*               |     r7      | 40  +0          |
*               |     r6      | 36              |
*               |     r5      | 32              |
*               |     r4      | 28              |
*               |     r3      | 24              |               +--------+
*               |     r2      | 20              |            r6 |REG_SET*|
*               |     r1      | 16              |               +--------+
*               |     r0      | 12              |            r5 | ESFSH *|
*               |     pr      |  8              |               +--------+
*               |     gbr     |  4              |            r4 |  INUM  |
*       r6 ---> |____ vbr ____|  0    __________v__             +--------+
*               |             |
*/
	.align	_ALIGN_TEXT
	.type	_fppProbeTrap,@function

_fppProbeTrap:
	mov	#-1,r0
	mov.l	r0,@(12,r6)	/* modify fppProbeSup() return value to ERROR */

	mov.l	@r5,r0		/* exception address in _fppProbeSup */
	add	#2,r0		/* skip 'fabs' */
	rts;			/* return to excStub */
	mov.l	r0,@r5		/* modify spc on stack */

#endif /* _WRS_HW_FP_SUPPORT */