windalib.s

vxworks source code, used for develop vxworks system.

/* windALib.s - internal VxWorks kernel assembly library */

/* Copyright 1995-2001 Wind River Systems, Inc. */

	.data
	.global	_copyright_wind_river
	.long	_copyright_wind_river

/*
modification history
--------------------
04q,10dec01,zl   added leading underscore to areWeNested.
04p,05nov01,zl   added underscore to intRte1W and intRte2W.
04o,07sep01,h_k  added _func_vxIdleLoopHook for power control support (SPR
                 #69838).
04n,24sep00,zl   moved _func_wdbUbcInit from wdbDbgArchLib.c.
04m,08sep00,hk   merge SH7729 to SH7700. merge SH7410 and SH7040 to SH7600.
		 rename brandNewTaskSR to intUnlockSR, also change it as
		 a global data to support SR.DSP preservation.
		 move windIntStackSet to intArchLib.
04l,21jun00,hk   rearranged code layout to improve WV-off performance.
04k,23may00,hk   fixed instrumentation bugs in windExitInt/checkWorkQ/dispatch.
04j,22may00,hk   reviewed WindView instrumentation code for T2/SH4.
04i,27apr00,frf  WindView support for SH: functions changed:reschedule,
		 idle,windExitInt,checkWorkQ,windExit,intEnt,intExit.
04h,10apr00,hk   got rid of .ptext/.pdata sections. relaxed tight coding.
04g,28mar00,hk   added .type directive to function names and variables.
04f,17mar00,zl   made use of alignment macro _ALIGN_TEXT
04e,05oct99,zl   updated for little endian event logging
04e,08jun99,zl   added .ptext attribute "ax" and .pdata attribute "aw"
04d,02mar99,hk   put back intCnt to intLib, errno to errnoLib.
04c,02mar99,hk   simplified CPU conditionals.
03y,07nov98,hk   changed intStub to facilitate intVecSet() usage by user.
04b,09oct98,hk   code review: sorted CPU conditionals.
04a,07oct98,st   changed to use SGR register at stack change operation in
		 intStub (SH7750 only).
03z,17sep98,hk   unified to use SH7700_VEC_TABLE_OFFSET for SH7750.
03y,16jul98,st   added SH7750 support.
03z,02sep98,jmc  revised initial SR for SH7729 to include DSP = 1.
03y,08may98,jmc  added support for SH-DSP and SH3-DSP.
03x,03mar98,hk   changed to use immediate values instead of longword constants.
03w,03nov97,hk   reviewed intExit instrumentation for SH7600/SH7040/SH7000.
03v,10jul97,hk   reviewed windview instrumentation code.
03u,11jun97,hms  deleted lines related with windview, as there were duplicate
                 instructions in sequence of intStub function.
03t,05may97,hk   deleted pre-03a history, see RCS. made windviewInstr local.
03s,03may97,hk   made windview instrumentation conditionally compiled.
03r,28apr97,hk   changed SH704X to SH7040.
03t,11apr97,hms  added variable reference for SH7600/7000/704X WindView support
03s,16mar97,hms  changed function order. Functions for WindView suppport were
		 move to top of this file.
03r,06mar97,hms  added WindView support.
03q,12feb97,hk   added SH7707 support, intStub selects INTEVT2 by intEvtAdrs.
                 pushed INTEVT on stack to avoid r4_bank1 corruption by NMI.
03p,18jan97,hk   added _nullEvtCnt to monitor null event interrupt.
03o,23dec96,hk   changed code layout to localize pc relative labels. deleted
                 unnecessary .align and 68k specific comments. did pipeline
                 optimization in intRte and saveIntContext for SH7700. moved
                 _vxTaskEntry/_windIntStackSet back to .text.
03n,22dec96,hk   updated windLoadContext for SH7700. did some comment review.
03m,21dec96,hk   moved vxIntStackBase/intCnt/errno to .pdata.
03l,16dec96,wt   deleted DEBUG_LOCAL_LABELS stuff. made VxIntStackBase and
           +hk   AreWeNested local. made windIntStackSet as empty function.
03k,16dec96,wt   changed dispatch for mmu support. removed logical memory
           +hk   access code after blocking TLB exception. 
03j,12dec96,hk   named .ptext/.pdata sections for SH7700 mmu support.
03i,09dec96,hk   made areWeNested global, set INTEVT to r4_bank1 in intStub,
		 added intStayBlocked: to handle NULL entry in intPrioTable[].
03h,08dec96,wt   changed intStub/intExit/saveIntContext for SH7700 to run
	   +hk   interrupt handler on bank-0. adopt areWeNested for SH7700.
03g,26sep96,hk   added interrupt blocking code in dispatch. changed cmp/eq to
		 tst in intUnblock, to use r2 instead of r0. rewrote intExit
		 for SH7700, now its sequence is identical to SH7600/SH7000.
03f,17sep96,hk   overhauled _intStub, added bypass for BL unblocking.
03e,02sep96,hk   deleted unnecessary comment.
03d,23aug96,hk   changed INTEVT notation (-40 => 0xd8).
03c,19aug96,hk   deleted INT_STACK_ENABLE, intSpurious, moved SH7700 intRte.
03b,19aug96,hk   changed code align to save some bytes.
03a,18aug96,hk   improved interrupt stack emulation for SH7600/SH7000/SH7040.
*/

/*
DESCRIPTION
This module contains internals to the VxWorks kernel.
These routines have been coded in assembler because they are either
specific to this processor, or they have been optimized for performance.

INTERNAL

        +-----> checkTaskReady
        |               |
        |               +--(task is not ready)------------------------->+
        |               |                                               |
        |               v                                               |
        |  +--> checkWorkQ                            windExitInt <--+  |
        |  |            |                               |            |  |
        |  |            +---->(workQueue is empty)<-----+            |  |
        |  |            |               |               |            |  |
        |  |            |               v               |            |  |
        |  |            |             return            |            |  |
        |  |            v                               v            |  |
        |  |    doWorkPreSave <=> _workQDoWork <=> windExitIntWork   |  |
        |  |            |                               |            |  |
        |  |            |   _windExit                   +----------->|  |
        |  |            |       |                                    |  |
        |  |            |       +----(called at interrupt level)---->+  |
        |  |            |       |                                       |
        |  |            v       v                                       v
        |  |          checkTaskSwitch   +-------------------------------+
        |  |                    |       |
        |  +--(task is highest)-+       |    _intExit
        |                       |       |       |
        +-----(task is locked)--+       |       +--> intRte -> rte
                                |       |       |
                                v       v       v
                             saveTaskContext    saveIntContext
                                        |       |
                                        v       v
                                        reschedule
                                            |
        +--------------------+              v
        | windExit & intExit |       _windLoadContext
        | state transition   |              |
        | diagram            |              v
        +--------------------+             rte (to new context)
*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "iv.h"
#include "private/taskLibP.h"
#include "private/workQLibP.h"
#include "private/eventP.h"
#include "private/semLibP.h"

#if	(TRG_CLASS1_INDEX > 0x7f)
#error	TRG_CLASS1_INDEX > 0x7f, check eventP.h
#endif
#if	(MIN_INT_ID >= 0x7f)
#error	MIN_INT_ID >= 0x7f, check eventP.h
#endif
#if	(EVENT_DISPATCH_OFFSET >= 0x7f)
#error	EVENT_DISPATCH_OFFSET >= 0x7f, check eventP.h
#endif
#if	(EVENT_INT_EXIT >= 0x7f)
#error	EVENT_INT_EXIT >= 0x7f, check eventP.h
#endif
#if	(EVENT_INT_EXIT_K >= 0x7f)
#error	EVENT_INT_EXIT_K >= 0x7f, check eventP.h
#endif
#if	(EVENT_NODISPATCH_OFFSET >= 0x7f)
#error	EVENT_NODISPATCH_OFFSET >= 0x7f, check eventP.h
#endif
#if	(EVENT_WIND_EXIT_DISPATCH >= 0x7f)
#error	EVENT_WIND_EXIT_DISPATCH >= 0x7f, check eventP.h
#endif
#if	(EVENT_WIND_EXIT_DISPATCH_PI >= 0x7f)
#error	EVENT_WIND_EXIT_DISPATCH_PI >= 0x7f, check eventP.h
#endif
#if	(EVENT_WIND_EXIT_NODISPATCH >= 0x7f)
#error	EVENT_WIND_EXIT_NODISPATCH >= 0x7f, check eventP.h
#endif
#if	(EVENT_WIND_EXIT_NODISPATCH_PI >= 0x7f)
#error	EVENT_WIND_EXIT_NODISPATCH_PI >= 0x7f, check eventP.h
#endif
#if	(EVENT_WIND_EXIT_IDLE >= 0x7f)
#error	EVENT_WIND_EXIT_IDLE >= 0x7f, check eventP.h
#endif
#if	(WIND_TCB_ENTRY >= 0x7f)
#error	WIND_TCB_ENTRY >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_ERRNO >= 0x7f) && FALSE
#error	WIND_TCB_ERRNO >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_LOCK_CNT >= 0x7f)
#error	WIND_TCB_LOCK_CNT >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_PRIORITY >= 0x7f)
#error	WIND_TCB_PRIORITY >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_PRI_NORMAL >= 0x7f)
#error	WIND_TCB_PRI_NORMAL >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_STATUS >= 0x7f)
#error	WIND_TCB_STATUS >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_SWAP_IN >= 0x7f)
#error	WIND_TCB_SWAP_IN >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_SWAP_OUT >= 0x7f)
#error	WIND_TCB_SWAP_OUT >= 0x7f, check taskLibP.h
#endif
#if	(WIND_TCB_MACL > 0x7fff)
#error	WIND_TCB_MACL > 0x7fff, check regsSh.h and taskLibP.h
#endif

#if (CPU==SH7750 || CPU==SH7700)

#if	(SH7700_INT_EVT_ADRS_OFFSET > 60)
#error	SH7700_INT_EVT_ADRS_OFFSET > 60, check ivSh.h
#endif
#if	(SH7700_ARE_WE_NESTED_OFFSET > 60)
#error	SH7700_ARE_WE_NESTED_OFFSET > 60, check ivSh.h
#endif
#if	(SH7700_INT_STACK_BASE_OFFSET > 60)
#error	SH7700_INT_STACK_BASE_OFFSET > 60, check ivSh.h
#endif
#if	(SH7700_NULL_EVT_CNT_OFFSET > 60)
#error	SH7700_NULL_EVT_CNT_OFFSET > 60, check ivSh.h
#endif
#if	(SH7700_DISPATCH_STUB_OFFSET > 0x7f)
#error	SH7700_DISPATCH_STUB_OFFSET > 0x7f, check ivSh.h and adjust dispatch.
#endif
#if	(SH7700_INT_EXIT_STUB_OFFSET > 0x7f)
#error	SH7700_INT_EXIT_STUB_OFFSET > 0x7f, check ivSh.h and adjust intExit.
#endif

#define INT_EVT_ADRS	SH7700_INT_EVT_ADRS_OFFSET		/* ivSh.h */
#define ARE_WE_NESTED	SH7700_ARE_WE_NESTED_OFFSET		/* ivSh.h */
#define INT_STACK_BASE	SH7700_INT_STACK_BASE_OFFSET		/* ivSh.h */
#define NULL_EVT_CNT	SH7700_NULL_EVT_CNT_OFFSET		/* ivSh.h */
#define DISPATCH_STUB	SH7700_DISPATCH_STUB_OFFSET		/* ivSh.h */
#define INT_EXIT_STUB	SH7700_INT_EXIT_STUB_OFFSET		/* ivSh.h */

#elif (CPU!=SH7600 && CPU!=SH7000)
#error The CPU macro is not defined properly
#endif /* CPU!=SH7600 && CPU!=SH7000 */

/* 
 * The _func_wdbUbcInit declaration normally should be in wdbDbgArchLib.c, but
 * then bootrom builds fail because the BSPs setting this function pointer drag
 * in the wdbDbgArchLib.o module.
 */

	.global __func_wdbUbcInit
	.type	__func_wdbUbcInit,@object
	.align 2
__func_wdbUbcInit:	.long	0	/* hook for BSP's UBC init function */

	.text

	.global	_windExit		/* routine to exit mutual exclusion */
	.global	_vxTaskEntry		/* task entry wrapper           */
	.global	_intExit		/* interrupt exit routine       */
	.global	_intEnt			/* interrupt entrance routine   */
#if (CPU==SH7750 || CPU==SH7700)
	.global	_dispatchStub		/* referenced from intArchLib	*/
	.global	_dispatchStubSize	/* referenced from intArchLib	*/
	.global	_intExitStub		/* referenced from intArchLib	*/
	.global	_intExitStubSize	/* referenced from intArchLib	*/
	.global	_intStub		/* referenced from intArchLib   */
	.global	_intStubSize		/* referenced from intArchLib   */
	.global	_intRte1W		/* for intVecSet() usage */
	.global	_intRte2W		/* for intVecSet() usage */
#endif /* CPU==SH7750 || CPU==SH7700 */

#undef	DEBUG
#ifdef	DEBUG
	.global	windExitInt
	.global	checkTaskReady
	.global	checkWorkQ
	.global	doWorkPreSave
	.global	checkTaskSwitch
	.global	saveTaskContext
	.global	saveIntContext
#ifdef	WV_INSTRUMENTATION
	.global	intEntInstr
	.global	intExitInstr
	.global	noDispatchInstr
#endif	/* WV_INSTRUMENTATION */
#endif	/* DEBUG */

#undef	PORTABLE
#ifdef	PORTABLE
	.global	_windLoadContext	/* needed by portable reschedule () */
#else	/* !PORTABLE */
	.global	_reschedule		/* optimized reschedule () routine */
#ifdef	DEBUG
	.global	idle
	.global	switchTasks
	.global	doSwapHooks
	.global	doSwitchHooks
	.global	dispatch
	.global	doWorkUnlock
	.global	doWork
#ifdef	WV_INSTRUMENTATION
	.global	dispatchInstr
	.global	idleInstr
#endif	/* WV_INSTRUMENTATION */
#endif	/* DEBUG */
#endif	/* !PORTABLE */


#if (CPU==SH7750 || CPU==SH7700)
/******************************************************************************
*
* dispatchStub - last part of task dispatch (SH7750/SH7700)
*
* Before loading spc/ssr, intRte must set SR.BL to 1.  While SR.BL=1,
* any virtual space access may cause h/w reboot due to TLB miss hit.
* Hence this routine is copied to a fixed physical address space.
*
* NOTE: This stub is shared by dispatch/windLoadContext/_sigCtxLoad.
*/
	.align	2			/* ??? hangs if no align */
	.type	_dispatchStub,@function

_dispatchStub:				/* SR: intLockTaskSR */
	mov.l	@r14+,r11
	mov.l	@r14+,r12
	mov.l	@r14+,r13
	ldc.l	@r14+,r4_bank
	ldc.l	@r14+,r5_bank
	ldc.l	@r14+,r6_bank
	ldc.l	@r14+,r7_bank

	mov.l	DS_IntBlockSR,r14
	mov.l	@r14,r14
	ldc	r14,sr			/* BLOCK INTERRUPTS/EXCEPTION, RB=1 */

	mov	r4,r14
	mov	r5,sp
	ldc	r6,spc
	ldc	r7,ssr
	rte;				/* UNBLOCK INTERRUPTS/EXCEPTION */
	nop
			.align	2
DS_IntBlockSR:		.long	_intBlockSR
dispatchStubEnd:
			.align	2
			.type	_dispatchStubSize,@object
			.size	_dispatchStubSize,4
_dispatchStubSize:	.long	dispatchStubEnd - _dispatchStub

/******************************************************************************
*
* intExitStub - last part of intExit (SH7750/SH7700)
*
* Before loading spc/ssr, SR.BL must be set to 1.  While SR.BL=1,
* any virtual space access may cause h/w reboot due to TLB miss hit.
* Hence this routine is copied to a fixed physical address space.
*/
	.align	2			/* ??? hangs if no align */
	.type	_intExitStub,@function

_intExitStub:
	/* BLOCK INTS/EXCEPTION */	mov.l	@sp+,r1
	ldc	r0,sr;			ldc.l	@sp+,r0_bank
					lds.l	@sp+,pr
intRte2:
	stc	vbr,r1;			ldc.l	@sp+,spc
	mov.l	@(ARE_WE_NESTED,r1),r0; ldc.l	@sp+,ssr
	rotr	r0
	bf.s	intRteNested;
	mov.l	r0,@(ARE_WE_NESTED,r1)	/* update areWeNested */
	rte;
	mov.l	@(4,sp),sp		/* return to task stack */

intRteNested:
	rte;
	add	#4,sp			/* skip INTEVT */

intRte1:				mov.l	@sp+,r1
	ldc	r0,sr;			bra	intRte2;
					ldc.l	@sp+,r0_bank
intExitStubEnd:
			.align	2
			.type	_intExitStubSize,@object
			.size	_intExitStubSize,4
_intExitStubSize:	.long	intExitStubEnd - _intExitStub


/* 
 * _intRte1W and _intRte2W can be used to implement fast interrupt handlers
 * connected with intVecSet() as described in target/src/arch/doc/intArchLib.c
 */


		.type	_intRte1W,@object
		.size	_intRte1W,2
_intRte1W:	.word	intRte1 - _intExitStub + INT_EXIT_STUB

		.type	_intRte2W,@object
		.size	_intRte2W,2
_intRte2W:	.word	intRte2 - _intExitStub + INT_EXIT_STUB


/******************************************************************************
*
* intStub - Catch and dispatch interrupts (SH7750/SH7700)
*
* This is the interrupt dispatcher that is pointed to by the SH3 interrupt
* vector.  These instructions are copied to (vbr + 0x600), the SH3 interrupt
* vector by the startup routine intVecBaseSet().  In this routine we take care
* of saving state, and jumping to the appropriate routine.  On exit from
* handling we also return here to restore state properly.
*
* NOMANUAL

* void intStub()

* INTERNAL
*
*    [ task's stack ]		   [ interrupt stack ]
*				
*	|  xxx	|
*	|  yyy	|     vxIntStackBase ->	+-------+
*	|__zzz__|<----------------------|task'sp| +8
*	|	|			|INTEVT	| +4
*	|	|			|  ssr	| +0 (at intStubNullEvt)
*				  sp ->	|_ spc _|
*					|	|
*
* CAUTION: DO NOT BREAK R4, R5, R6, AND R7 IN BANK1 !!!