iic.h

umon bootloader source code, support mips cpu.

#include "risc.h"

#define IIC_WAIT_TIME   10000
#define IIC_PUSH_DELAY  10//2

#define rIIC_SDA_BIT_REG            (*(volatile unsigned *)(0xa8000080))
#define rIIC_SDA_BIT_SHIFT          9
#define rIIC_SDA_DIR_BIT_REG        (*(volatile unsigned *)(0xa8000084))
#define rIIC_SDA_DIR_BIT_SHIFT      9
#define rIIC_SCL_BIT_REG            (*(volatile unsigned *)(0xa8000080))
#define rIIC_SCL_BIT_SHIFT          10
#define rIIC_SCL_DIR_BIT_REG        (*(volatile unsigned *)(0xa8000084))
#define rIIC_SCL_DIR_BIT_SHIFT      10

//ak8817
#define AK8817_I2C_ADDR        			0x20 //0x40
#define CTL_1_REG               0x00
#define CTL_2_REG               0x01
#define VBID_WSS_1_REG          0x02
#define VBID_WSS_2_REG          0x03
#define INPUT_CTL_REG           0x04
#define	ID_REG									0x05

#define AK8817_RESET_BIT_REG            (*(volatile unsigned *)(0xa8000080))
#define AK8817_RESET_BIT_SHIFT          5
#define AK8817_RESET_DIR_BIT_REG        (*(volatile unsigned *)(0xa8000084))
#define AK8817_RESET_DIR_BIT_SHIFT      5

#define AK8817_RESET_OUT()			(AK8817_RESET_DIR_BIT_REG &= ~(0x1 << AK8817_RESET_DIR_BIT_SHIFT))
#define AK8817_RESET_SET()       (AK8817_RESET_BIT_REG |= (0x1 << AK8817_RESET_BIT_SHIFT))
#define AK8817_RESET_CLR()       (AK8817_RESET_BIT_REG &= ~(0x1 << AK8817_RESET_BIT_SHIFT))


/* data line direction control macro */
#define IIC_SDA_OUT()				(rIIC_SDA_DIR_BIT_REG &= ~(0x1 << rIIC_SDA_DIR_BIT_SHIFT))
#define IIC_SDA_IN()        (rIIC_SDA_DIR_BIT_REG |= (0x1 << rIIC_SDA_DIR_BIT_SHIFT))
/* data line level control marco */
#define IIC_SDA_SET()       (rIIC_SDA_BIT_REG |= (0x1 << rIIC_SDA_BIT_SHIFT))
#define IIC_SDA_CLR()       (rIIC_SDA_BIT_REG &= ~(0x1 << rIIC_SDA_BIT_SHIFT))
#define IIC_SDA_GET()       ((rIIC_SDA_BIT_REG >> rIIC_SDA_BIT_SHIFT) & 0x1)
/* clock line direction control macro */
#define IIC_SCL_OUT()       (rIIC_SCL_DIR_BIT_REG &= ~(0x1 << rIIC_SCL_DIR_BIT_SHIFT))
#define IIC_SCL_IN()        (rIIC_SCL_DIR_BIT_REG |= (0x1 << rIIC_SCL_DIR_BIT_SHIFT))
/* clock line level control marco */
#define IIC_SCL_SET()       (rIIC_SCL_BIT_REG |= (0x1 << rIIC_SCL_BIT_SHIFT))
#define IIC_SCL_CLR()       (rIIC_SCL_BIT_REG &= ~(0x1 << rIIC_SCL_BIT_SHIFT))

#define IIC_ACK_ERROR   -1
#define IIC_ACK_SUCCESS 1
#define IIC_ERROR   -1
#define IIC_OK      1

void IICDelayLoop();
void IICDelay(int cnt);
void IICinit(void);
void IICStart(void);         /* statr the iic bus */
void IICStop(void);          /* stop the iic bus */

void IICWrite(int buf);      /* write the iic bus */
int IICChkAck(void);         /* chack the acknowledge signel */


int IICWriteByte(int SlaveAddr, int ByteAddr, int data, int mode);
void ak8817_reset(void);