arch_ppc.h

umon bootloader source code, support mips cpu.

/*
 * arch_ppc.h:
 *
 * Some of this is from IBM BSP source code...
 *
 * This source code has been made available to you by IBM on an AS-IS
 * basis.  Anyone receiving this source is licensed under IBM
 * copyrights to use it in any way he or she deems fit, including
 * copying it, modifying it, compiling it, and redistributing it either
 * with or without modifications.  No license under IBM patents or
 * patent applications is to be implied by the copyright license.
 *
 * Any user of this software should understand that IBM cannot provide
 * technical support for this software and will not be responsible for
 * any consequences resulting from the use of this software.
 *
 * Any person who transfers this source code or any derivative work
 * must include the IBM copyright notice, this paragraph, and the
 * preceding two paragraphs in the transferred software.
 *
 * COPYRIGHT   I B M   CORPORATION 1995
 * LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 *
 *	General notice:
 *	This code is part of a boot-monitor package developed as a generic base
 *	platform for embedded system designs.  As such, it is likely to be
 *	distributed to various projects beyond the control of the original
 *	author.  Please notify the author of any enhancements made or bugs found
 *	so that all may benefit from the changes.  In addition, notification back
 *	to the author will allow the new user to pick up changes that may have
 *	been made by other users after this version of the code was distributed.
 *
 *	Note1: the majority of this code was edited with 4-space tabs.
 *	Note2: as more and more contributions are accepted, the term "author"
 *		   is becoming a mis-representation of credit.
 *
 *	Original author:	Ed Sutter
 *	Email:				[e-mail]
 *	Phone:				[phone]
 * 
 */

#ifndef MW
 #define	sp   1
 #define	r0   0
 #define	r1   1
 #define	r2   2
 #define	r3   3
 #define	r4   4
 #define	r5   5
 #define	r6   6
 #define	r7   7
 #define	r8   8
 #define	r9   9
 #define	r10   10
 #define	r11   11
 #define	r12   12
 #define	r13   13
 #define	r14   14
 #define	r15   15
 #define	r16   16
 #define	r17   17
 #define	r18   18
 #define	r19   19
 #define	r20   20
 #define	r21   21
 #define	r22   22
 #define	r23   23
 #define	r24   24
 #define	r25   25
 #define	r26   26
 #define	r27   27
 #define	r28   28
 #define	r29   29
 #define	r30   30
 #define	r31   31
#endif

/*
 * Floating Point Registers
 */
 #define	fr0   0
 #define	fr1   1
 #define	fr2   2
 #define	fr3   3
 #define	fr4   4
 #define	fr5   5
 #define	fr6   6
 #define	fr7   7
 #define	fr8   8
 #define	fr9   9
 #define	fr10   10
 #define	fr11   11
 #define	fr12   12
 #define	fr13   13
 #define	fr14   14
 #define	fr15   15
 #define	fr16   16
 #define	fr17   17
 #define	fr18   18
 #define	fr19   19
 #define	fr20   20
 #define	fr21   21
 #define	fr22   22
 #define	fr23   23
 #define	fr24   24
 #define	fr25   25
 #define	fr26   26
 #define	fr27   27
 #define	fr28   28
 #define	fr29   29
 #define	fr30   30
 #define	fr31   31

/*
 * Special Purpose Registers
 */
 #define	xer		0x01		/*  fixed point exception register */
 #define	lr		0x08		/*  link register */
 #define	ctr		0x09		/*  count register */
 #define	srr0	0x1a		/*  save/restore register 0 */
 #define	srr1	0x1b		/*  save/restore register 1 */
 #define	dec		22			/*  decrementer register */
 #define	sprg0	272			/*  special general reg 0 */
 #define	sprg1	273			/*  special general reg 1 */
 #define	sprg2	274			/*  special general reg 2 */
 #define	sprg3	275			/*  special general reg 3 */
 #define	pvr		287			/*  processor version */

/*
 * Machine State Register     msr     Bit Masks
 */
 #define	pow   0x40000        /* Activates power management */
 #define	ile   0x10000        /* Interrupt little Endian */
 #define	ee   0x8000          /* external interrupt*/
 #define	pr   0x4000          /* problem state  */
 #define	fp   0x2000          /* floating point available */
 #define	me   0x1000          /* machine check */
 #define	fe0   0x0800         /* floating  point exception enable */
 #define	se   0x0400          /* single step trace enable*/
 #define	be   0x0200          /* branch trace enable*/
 #define	fe1   0x0100         /* floating  point exception enable*/
 #define	ip   0x0040          /* prefix */
 #define	ir   0x0020          /* instruction relocate*/
 #define	dr   0x0010          /* data relocate*/
 #define	ri   0x0002          /* recoverable exception */
 #define	le   0x0001          /* Little Endian mode */
 #define	MSR_EE   0x8000      /* external interrupt*/
 #define	MSR_PR   0x4000      /* problem state*/
 #define	MSR_FP   0x2000      /* floating point available*/
 #define	MSR_ME   0x1000      /* machine check*/
 #define	MSR_FE0   0x0800     /* floating point exception enable*/
 #define	MSR_SE   0x0400      /* single step trace enable*/
 #define	MSR_FE1   0x0100     /* floating point exception enable*/
 #define	MSR_EP   0x0040      /* prefix*/
 #define	MSR_IR   0x0020      /* instruction relocate*/
 #define	MSR_DR   0x0010      /* data relocate*/
 #define	MSR_RI   0x0002      /* Recoverable interrupt */
 #define	MSR_LE   0x0001      /* Little Endian */


/*
 * Branch Conditions
 */
 #define	false   0x04       /*branch false bo */
 #define	true   0x0c        /*branch true bo*/
 #define	falsectr   0x00    /*dec ctr branch false and ctr != 0 bo*/
 #define	falzezct   0x02    /*dec ctr branch false and ctr  = 0 bo*/
 #define	truectr   0x08     /*dec ctr branch true  and ctr != 0 bo*/
 #define	truezctr   0x0a    /*dec ctr branch true  and ctr  = 0 bo*/
 #define	always   0x14      /*branch unconditional bo*/
 #define	brctr   0x10       /*dec ctr    branch ctr != 0 bo */
 #define	brzctr   0x12      /*dec ctr    branch ctr  = 0 bo */
 #define	lt   0x00          /*less than condition     bit 0   */
 #define	gt   0x01          /*greater than condition     bit 1  */
 #define	eq   0x02          /*equal condition     bit 2 from 0 */
 #define	so   0x03          /*so bit in cr     bit 3  */
 #define	nolk   0x00        /*no link*/
 #define	lk   0x01          /*link*/

/*
 * Branch Conditions Alternate definitions
 */
 #define	BO_dCTR_NZERO_AND_NOT   0
 #define	BO_dCTR_NZERO_AND_NOT_1   1
 #define	BO_dCTR_ZERO_AND_NOT   2
 #define	BO_dCTR_ZERO_AND_NOT_1   3
 #define	BO_IF_NOT   4
 #define	BO_IF_NOT_1   5
 #define	BO_IF_NOT_2   6
 #define	BO_IF_NOT_3   7
 #define	BO_dCTR_NZERO_AND   8
 #define	BO_dCTR_NZERO_AND_1   9
 #define	BO_dCTR_ZERO_AND   10
 #define	BO_dCTR_ZERO_AND_1   11
 #define	BO_IF   12
 #define	BO_IF_1   13
 #define	BO_IF_2   14
 #define	BO_IF_3   15
 #define	BO_dCTR_NZERO   16
 #define	BO_dCTR_NZERO_1   17
 #define	BO_dCTR_ZERO   18
 #define	BO_dCTR_ZERO_1   19
 #define	BO_ALWAYS   20
 #define	BO_ALWAYS_1   21
 #define	BO_ALWAYS_2   22
 #define	BO_ALWAYS_3   23
 #define	BO_dCTR_NZERO_8   24
 #define	BO_dCTR_NZERO_9   25
 #define	BO_dCTR_ZERO_8   26
 #define	BO_dCTR_ZERO_9   27
 #define	BO_ALWAYS_8   28
 #define	BO_ALWAYS_9   29
 #define	BO_ALWAYS_10   30
 #define	BO_ALWAYS_11   31
/*
 * Condition Register Bit Fields
 */
#ifndef MW
 #define	cr0   0
 #define	cr1   1
 #define	cr2   2
 #define	cr3   3
 #define	cr4   4
 #define	cr5   5
 #define	cr6   6
 #define	cr7   7
#endif

/*
 * Condition Register Bit Sub-fields
*/

#define	cr0_0   0
#define	cr0_1   1
#define	cr0_2   2
#define	cr0_3   3

#define	cr1_0   4
#define	cr1_1   5
#define	cr1_2   6
#define	cr1_3   7

#define	cr2_0   8
#define	cr2_1   9
#define	cr2_2   10
#define	cr2_3   11

#define	cr3_0   12
#define	cr3_1   13
#define	cr3_2   14
#define	cr3_3   15

#define	cr4_0   16
#define	cr4_1   17
#define	cr4_2   18
#define	cr4_3   19

#define	cr5_0   20
#define	cr5_1   21
#define	cr5_2   22
#define	cr5_3   23

#define	cr6_0   24
#define	cr6_1   25
#define	cr6_2   26
#define	cr6_3   27

#define	cr7_0   28
#define	cr7_1   29
#define	cr7_2   30
#define	cr7_3   31
/*
 * Special Purpose Registers
 */
#define	zpr    0x3b0     /* zone protection register         (403GC) */
#define	pid    0x3b1     /* process id register              (403GC) */
#define	smr    0x3b8     /* storage mem-coherent (not implemented)   */
#define	sgr    0x3b9     /* storage guarded register         (403GC) */
#define	dcwr   0x3ba     /* data cache write-thru register   (403GC) */
#define	tbhu   0x3cc     /* user-mode time base high         (403GC) */
#define	tblu   0x3cd     /* user-mode time base low          (403GC) */
#define	icdbdr 0x3d3     /* instruction cache debug data reg (403GC) */
#define	esr    0x3d4     /* execption syndrome register              */
#define	dear   0x3d5     /* data exeption address register           */
#define	evpr   0x3d6     /* exeption vector prefix register          */
#define	cdbcr  0x3d7     /* cache debug control register     (403GC) */
#define	tsr    0x3d8     /* timer status register                    */
#define	tcr    0x3da     /* timer control register                   */
#define	pit    0x3db     /* programmable interval timer              */
#define	tbhi   0x3dc     /* time base high                           */
#define	tblo   0x3dd     /* time base low                            */
#define	srr2   0x3de     /* save/restore register 2                  */
#define	srr3   0x3df     /* save/restore register 3                  */
#define	dbsr   0x3f0     /* debug status register                    */
#define	dbcr   0x3f2     /* debug control register                   */
#define	dbcr0  0x3f2     /* debug control register 0 (405GP)         */
#define	dbcr1  0x3bd     /* debug control register 1 (405GP)         */
#define	iac1   0x3f4     /* instruction address comparator 1         */
#define	iac2   0x3f5     /* instruction address comparator 2         */
#define	iac3   0x3b4     /* instruction address comparator 3 (405GP) */
#define	iac4   0x3b5     /* instruction address comparator 4 (405GP) */
#define	dac1   0x3f6     /* data address comparator 1                */
#define	dac2   0x3f7     /* data address comparator 2                */
#define	dvc1   0x3b6     /* data value comparator 1 (405GP)          */
#define	dvc2   0x3b7     /* data value comparator 2 (405GP)          */
#define	dccr   0x3fa     /* data cache control register              */
#define	iccr   0x3fb     /* instruction cache control register       */
#define	pbl1   0x3fc     /* protection bound lower 1                 */
#define	pbu1   0x3fd     /* protection bound upper 1                 */
#define	pbl2   0x3fe     /* protection bound lower 2                 */
#define	pbu2   0x3ff     /* protection bound upper 2                 */


/*
 * Device Control Registers
 */
#define	exisr		0x40	/* external interrupt status register */
#define	exier		0x42	/* external interrupt enable register */
#define	br0			0x80	/* bank register 0 */
#define	br1			0x81	/* bank register 1 */
#define	br2			0x82	/* bank register 2 */
#define	br3			0x83	/* bank register 3 */
#define	br4			0x84	/* bank register 4 */
#define	br5			0x85	/* bank register 5 */
#define	br6			0x86	/* bank register 6 */
#define	br7			0x87	/* bank register 7 */
#define	bear		0x90	/* bus error address register */
#define	besr		0x91	/* bus error syndrome register */
#define	iocr		0xa0	/* input/output configuration register */
#define	dmacr0		0xc0	/* DMA channel control register 0 */
#define	dmact0		0xc1	/* DMA count register 0 */
#define	dmada0		0xc2	/* DMA destination address register 0 */
#define	dmasa0		0xc3	/* DMA source address register 0 */
#define	dmacc0		0xc4	/* DMA chained count 0 */
#define	dmacr1		0xc8	/* DMA channel control register 1 */
#define	dmact1		0xc9	/* DMA count register 1 */
#define	dmada1		0xca	/* DMA destination address register 1 */
#define	dmasa1		0xcb	/* DMA source address register 1  */
#define	dmacc1		0xcc	/* DMA chained count 1 */
#define	dmacr2		0xd0	/* DMA channel control register 2 */
#define	dmact2		0xd1	/* DMA count register 2 */
#define	dmada2		0xd2	/* DMA destination address register 2 */
#define	dmasa2		0xd3	/* DMA source address register 2  */
#define	dmacc2		0xd4	/* DMA chained count 2 */
#define	dmacr3		0xd8	/* DMA channel control register 3  */
#define	dmact3		0xd9	/* DMA count register 3 */
#define	dmada3		0xda	/* DMA destination address register 3 */
#define	dmasa3		0xdb	/* DMA source address register 3  */
#define	dmacc3		0xdc	/* DMA chained count 0 */
#define	dmasr		0xe0	/* DMA status register */

/*
 * Machine State Register   msr Bit Masks unique to 403GA
 */
#define	we  0x40000      /* wait state enable */
#define	ce  0x20000      /* critical interrupt enable */
#define	MSR_WE  0x40000  /* wait state enable */
#define	MSR_CE  0x20000  /* critical interrupt enable */
#define	MSR_DE  0x0200   /* debug enable */
#define	MSR_PE  0x0008   /* protection enable */
#define	MSR_PX  0x0004   /* protection exclusive mode */


#define	mtesr	mtspr esr,
#define	mtsrr2	mtspr srr2,
#define	mtsrr3	mtspr srr3,
#define	mtdcwr	mtspr dcwr,
#define	mttcr	mtspr tcr,
#define	mtevpr  mtspr evpr,
#define	mtsgr	mtspr sgr,
#define	mtdbsr	mtspr dbsr,
#define	mtdccr	mtspr dccr,
#define	mticcr	mtspr iccr,

#define	mtbr0	mtdcr br0,
#define	mtbr1	mtdcr br1,
#define	mtbr2	mtdcr br2,
#define	mtbr3	mtdcr br3,
#define	mtbr4	mtdcr br4,
#define	mtbr5	mtdcr br5,
#define	mtbr6	mtdcr br6,
#define	mtbr7	mtdcr br7,
#define	mtbesr	mtdcr besr,
#define	mtexier	mtdcr exier,
#define	mtexisr	mtdcr exisr,
#define	mtiocr	mtdcr iocr,

/* Note: if building with DIAB compiler, the "\reg", needs to be 
 * changed to "reg".
 */
#ifdef ASSEMBLY_ONLY
	.macro mfexisr	reg
		mfdcr	\reg,exisr
	.endm
	.macro mfexier	reg
		mfdcr	\reg,exier
	.endm
	.macro mfiocr	reg
		mfdcr	\reg,iocr
	.endm
	.macro mfesr	reg
		mfspr	\reg,esr