cpu_403.h

umon bootloader source code, support mips cpu.

*	cleared by being written to 1 by software.
*/

#define CPU_EXISR_CIS		0x80000000	/* Critical interrupt	*/
#define CPU_EXISR_SRIS		0x08000000	/* Serial port receive	*/
#define CPU_EXISR_STIS		0x04000000	/* Serial port transmit	*/
#define CPU_EXISR_JRIS		0x02000000	/* JTAG port receive	*/
#define CPU_EXISR_JTIS		0x01000000	/* JTAG port transmit	*/
#define CPU_EXISR_D0IS		0x00800000	/* DMA chan 0 interrupt	*/
#define CPU_EXISR_D1IS		0x00400000	/* DMA chan 1 interrupt	*/
#define CPU_EXISR_D2IS		0x00200000	/* DMA chan 2 interrupt	*/
#define CPU_EXISR_D3IS		0x00100000	/* DMA chan 3 interrupt	*/

#define CPU_EXISR_E0IS		0x00000010	/* External interrupt 0	*/
#define CPU_EXISR_E1IS		0x00000008	/* External interrupt 1	*/
#define CPU_EXISR_E2IS		0x00000004	/* External interrupt 2	*/
#define CPU_EXISR_E3IS		0x00000002	/* External interrupt 3	*/
#define CPU_EXISR_E4IS		0x00000001	/* External interrupt 4	*/

/*
*	I/O Configuration Register definitions.
*/

#define CPU_IOCR_E0T		0x80000000	/* Ext int 0 trigger	*/
#define CPU_IOCR_E0L		0x40000000	/* Ext int 0 level	*/
#define CPU_IOCR_E1T		0x20000000	/* Ext int 1 trigger	*/
#define CPU_IOCR_E1L		0x10000000	/* Ext int 1 level	*/
#define CPU_IOCR_E2T		0x08000000	/* Ext int 2 trigger	*/
#define CPU_IOCR_E2L		0x04000000	/* Ext int 2 level	*/
#define CPU_IOCR_E3T		0x02000000	/* Ext int 3 trigger	*/
#define CPU_IOCR_E3L		0x01000000	/* Ext int 3 level	*/
#define CPU_IOCR_E4T		0x00800000	/* Ext int 4 trigger	*/
#define CPU_IOCR_E4L		0x00400000	/* Ext int 4 level	*/
#define CPU_IOCR_EDT		0x00080000	/* Enable DRAM tri-state */
#define CPU_IOCR_SOR		0x00040000	/* Sample on READY	*/
#define CPU_IOCR_EDO		0x00008000	/* EDO DRAM enable	*/
#define CPU_IOCR_2XC		0x00004000	/* Clock-double core	*/
#define CPU_IOCR_ATC		0x00002000	/* Addr bus tri-state	*/
#define CPU_IOCR_SPD		0x00001000	/* Static power disable	*/
#define CPU_IOCR_BEM		0x00000800	/* Byte enable mode	*/
#define CPU_IOCR_PTD		0x00000400	/* Bus timeout disable	*/
#define CPU_IOCR_ARE		0x00000080	/* Asynchronous ready enable */
#define CPU_IOCR_DRC		0x00000020	/* DRAM read on CAS	*/
#define CPU_IOCR_RDM		0x00000018	/* Real-time debug mode	*/
#define CPU_IOCR_TCS		0x00000004	/* Timer clock source	*/
#define CPU_IOCR_SCS		0x00000002	/* Serial port clock source */
#define CPU_IOCR_SPC		0x00000001	/* Serial port configuration */

/*
*	I/O Configuration Register Real-Time Debug Mode definitions.
*/

#define CPU_IOCR_RDM_DISABLED	0x00000000	/* Trace port disabled	*/
#define CPU_IOCR_RDM_BUS		0x00000008	/* Bus status		*/
#define CPU_IOCR_RDM_TRACE		0x00000010	/* Trace output		*/
#define CPU_IOCR_RDM_PARITY		0x00000018	/* Byte parity		*/

/*
*	Machine State Register Definitions.
*/

#define CPU_MSR_WE		0x00040000	/* Wait state enable	*/
#define CPU_MSR_CE		0x00020000	/* Critical interrupt enable */
#define CPU_MSR_ILE		0x00010000	/* Interrupt low-endian	*/
#define CPU_MSR_EE		0x00008000	/* External interrupt enable */
#define CPU_MSR_PR		0x00004000	/* Problem (user) state	*/
#define CPU_MSR_ME		0x00001000	/* Machine check enable	*/
#define CPU_MSR_DE		0x00000200	/* Debug exception enable */
#define CPU_MSR_IR		0x00000020	/* Instruction relocate	*/
#define CPU_MSR_DR		0x00000010	/* Data relocate	*/
#define CPU_MSR_PE		0x00000008	/* Protection enable	*/
#define CPU_MSR_PX		0x00000004	/* Protection exclusive	*/
#define CPU_MSR_LE		0x00000001	/* Low-endian mode	*/

/*
*	Timer Control Register definitions.
*
*	All  bits  in this register are cleared by any form of reset.
*	After  that,  a  bit  that  has  been written to 1 can not be
*	written to 0.
*/

#define CPU_TCR_WP		0xc0000000	/* Watchdog period	*/
#define CPU_TCR_WRC		0x30000000	/* Watchdog reset control */
#define CPU_TCR_WIE		0x08000000	/* Watchdog interrupt enable */
#define CPU_TCR_PIE		0x04000000	/* PIT interrupt enable	*/
#define CPU_TCR_FP		0x03000000	/* FIT period		*/
#define CPU_TCR_FIE		0x00800000	/* FIT interrupt enable	*/
#define CPU_TCR_ARE		0x00400000	/* Auto reload enable	*/

/*
*	Timer Control Register Watchdog Period definitions.
*
*	The  times  noted, assume a 66 MHz core clock (doubled from a
*	33 MHz input).
*/

#define CPU_TCR_WP_17		0x00000000	/* About 2 msec.	*/
#define CPU_TCR_WP_21		0x40000000	/* About 32 msec.	*/
#define CPU_TCR_WP_25		0x80000000	/* About 1/2 second	*/
#define CPU_TCR_WP_29		0xc0000000	/* About 8 seconds	*/

/*
*	Timer Control Register Watchdog Reset definitions.
*/

#define CPU_TCR_WRC_CORE	0x10000000	/* Core reset		*/
#define CPU_TCR_WRC_CHIP	0x20000000	/* Chip reset		*/
#define CPU_TCR_WRC_SYSTEM	0x30000000	/* System reset		*/

/*
*	Timer Control Register FIT Period definitions.
*
*	The  times  noted, assume a 66 MHz core clock (doubled from a
*	33 MHz input).
*/

#define CPU_TCR_FP_9		0x00000000	/* About 8 usec.	*/
#define CPU_TCR_FP_13		0x01000000	/* About 128 usec.	*/
#define CPU_TCR_FP_17		0x02000000	/* About 2 msec.	*/
#define CPU_TCR_FP_21		0x03000000	/* About 32 msec.	*/

/*
*	Timer Status Register definitions.
*
*	Bits  in  this  register are set to 1 by hardware, and may be
*	cleared by being written to 1 by software.
*/

#define CPU_TSR_ENW		0x80000000	/* Enable next watchdog	*/
#define CPU_TSR_WIS		0x40000000	/* Watchdog interrupt status */
#define CPU_TSR_WRS		0x30000000	/* Watchdog reset status */
#define CPU_TSR_PIS		0x08000000	/* PIT interrupt status	*/
#define CPU_TSR_FIS		0x04000000	/* FIT interrupt status	*/

/*
*	Fixed Point Exception Register definitions.
*/

#define CPU_XER_SO		0x80000000	/* Summary overflow	*/
#define CPU_XER_OV		0x40000000	/* Overflow		*/
#define CPU_XER_CA		0x20000000	/* Carry		*/
#define CPU_XER_TBC		0x0000007f	/* Transfer byte count	*/

/*
*	Serial Port Unit Registers (Memory-Mapped).
*/

#define CPU_SPU_REG(n)	(*((volatile unsigned char *)((n)+0x40000000)))

#define CPU_SPU_SPLS	CPU_SPU_REG(0x0) /* Serial port line status	*/
#define CPU_SPU_SPHS	CPU_SPU_REG(0x2) /* Serial port handshake status */
#define CPU_SPU_BRDH	CPU_SPU_REG(0x4) /* Baud rate divisor high	*/
#define CPU_SPU_BRDL	CPU_SPU_REG(0x5) /* Baud rate divisor low	*/
#define CPU_SPU_SPCTL	CPU_SPU_REG(0x6) /* Serial port control		*/
#define CPU_SPU_SPRC	CPU_SPU_REG(0x7) /* Serial port receiver command */
#define CPU_SPU_SPTC	CPU_SPU_REG(0x8) /* Serial port transmitter command */
#define CPU_SPU_SPRB	CPU_SPU_REG(0x9) /* Serial port receive buffer	*/
#define CPU_SPU_SPTB	CPU_SPU_REG(0x9) /* Serial port transmit buffer	*/

/*
*	Serial Port Control Register definitions.
*/

#define CPU_SPCTL_LM		0xc0	/* Loopback modes		*/
#define CPU_SPCTL_DTR		0x20	/* DTR activate			*/
#define CPU_SPCTL_RTS		0x10	/* RTS activate			*/
#define CPU_SPCTL_DB		0x08	/* Number of data bits (7/8)	*/
#define CPU_SPCTL_PE		0x04	/* Parity enable		*/
#define CPU_SPCTL_PTY		0x02	/* Parity (even/odd)		*/
#define CPU_SPCTL_SB		0x01	/* Stop bits (1/2)		*/

/*
*	Serial Port Control Register loopback mode definitions.
*/

#define CPU_SPCTL_LM_NONE		0x00	/* No loopback			*/
#define CPU_SPCTL_LM_INTERNAL	0x40	/* Internal loopback		*/
#define CPU_SPCTL_LM_AUTOECHO	0x80	/* Automatic echo mode		*/

/*
*	Serial Port Control Register number of data bits definitions.
*/

#define CPU_SPCTL_DB_7		0x00	/* 7 data bits                  */
#define CPU_SPCTL_DB_8		0x08	/* 8 data bits                  */

/*
*	Serial Port Control Register parity settings
*/

#define CPU_SPCTL_PTY_EVEN	0x00	/* Even parity                  */
#define CPU_SPCTL_PTY_ODD	0x02	/* Odd parity                   */

/*
*	Serial Port Control Register number of stop bits
*/

#define CPU_SPCTL_SB_1		0x00	/* 1 stop bit                   */
#define CPU_SPCTL_SB_2		0x01	/* 2 stop bits                  */

/*
*	Serial Port Handshake Register definitions.
*
*	Bits  in  this  register are set to 1 by hardware, and may be
*	cleared by being written to 1 by software.
*/

#define CPU_SPHS_DIS		0x80	/* DSR has gone inactive	*/
#define CPU_SPHS_CS			0x40	/* CTS has gone inactive	*/

/*
*	Serial Port Line Status Register definitions.
*
*	The  CPU_SPLS_FE,  CPU_SPLS_OE,  CPU_SPLS_PE, and CPU_SPLS_LB
*	bits are set when the indicated condition occurs, and must be
*	reset by being written to 1 by software.
*/

#define CPU_SPLS_RBR		0x80	/* Receive buffer ready		*/
#define CPU_SPLS_FE			0x40	/* Framing error		*/
#define CPU_SPLS_OE			0x20	/* Overrun error		*/
#define CPU_SPLS_PE			0x10	/* Parity error			*/
#define CPU_SPLS_LB			0x08	/* Line break			*/
#define CPU_SPLS_TBR		0x04	/* Transmit buffer ready	*/
#define CPU_SPLS_TSR		0x02	/* Transmit shift register ready */

/*
*	Serial Port Receiver Command Register definitions.
*/

#define CPU_SPRC_ER			0x80	/* Enable receiver		*/
#define CPU_SPRC_DME		0x60	/* DMA mode or interrupt enable	*/
#define CPU_SPRC_EIE		0x10	/* Error interrupt enable	*/
#define CPU_SPRC_PME		0x08	/* Pause mode enable (flow control) */

/*
*	Serial Port Receiver Command Register DMA mode definitions.
*/

#define CPU_SPRC_DME_NONE	0x00	/* No DMA, interrupt disabled	*/
#define CPU_SPRC_DME_INT	0x20	/* No DMA, interrupt enabled	*/
#define CPU_SPRC_DME_DMA2	0x40	/* Receive using DMA channel 2	*/
#define CPU_SPRC_DME_DMA3	0x60	/* Receive using DMA channel 3	*/

/*
*	Serial Port Transmitter Command Register definitions.
*/

#define CPU_SPTC_ET			0x80	/* Enable transmitter		*/
#define CPU_SPTC_DME		0x60	/* DMA mode or interrupt enable	*/
#define CPU_SPTC_TIE		0x10	/* Underrun interrupt enable	*/
#define CPU_SPTC_EIE		0x08	/* Error interrupt enable	*/
#define CPU_SPTC_SPE		0x04	/* Stop/pause enable		*/
#define CPU_SPTC_TB			0x02	/* Transmit break		*/
#define CPU_SPTC_PGM		0x01	/* Pattern generation mode	*/

/*
*	Serial Port Transmitter Command Register DMA mode definitions.
*/

#define CPU_SPTC_DME_NONE	0x00	/* No DMA, interrupt disabled	*/
#define CPU_SPTC_DME_INT	0x20	/* No DMA, interrupt enabled	*/
#define CPU_SPTC_DME_DMA2	0x40	/* Transmit using DMA channel 2	*/
#define CPU_SPTC_DME_DMA3	0x60	/* Transmit using DMA channel 3	*/

/*******************************************************************************
*
*	End of cpu403.h
*
*******************************************************************************/
#endif	/* CPU403_H */