cpu_403.h

umon bootloader source code, support mips cpu.

#define CPU_BR_SRAM_WBN		0x00000020	/* Write byte enable timing */
#define CPU_BR_SRAM_WBF		0x00000010	/* Write byte disable timing */
#define CPU_BR_SRAM_TH		0x0000000e	/* Transfer hold	*/

/*
*	Bank Register SRAM transfer value macros.
*
*	For CPU_BR_SRAM_BURST, the maximum values are:
*
*		f <= 15		Wait states on first transfer.
*		n <= 3		Wait states on subsequent transfers.
*		h <= 7		Idle bus cycles at end of transfer.
*
*	For CPU_BR_SRAM_NOBURST, the maximum values are:
*
*		n <= 63		Wait states on single transfer.
*		h <= 7		Idle bus cycles at end of transfer.
*
*	Note that the CPU_BR_SRAM_BURST macro sets the CPU_BR_BME bit.
*/

#define CPU_BR_SRAM_BURST(f,n,h) (0x00020000|((f)<<10)|((n)<<8)|((h)<<1))
#define CPU_BR_SRAM_NOBURST(n,h) (((n)<<8)|((h)<<1))

/*
*	Bank Register DRAM bus definitions.
*/

#define CPU_BR_DRAM_ERM		0x00020000	/* Early RAS mode	*/
#define CPU_BR_DRAM_IEM		0x00004000	/* External multiplex	*/
#define CPU_BR_DRAM_RCT		0x00002000	/* RAS-to-CAS timing	*/
#define CPU_BR_DRAM_ARM		0x00001000	/* Alternate refresh	*/
#define CPU_BR_DRAM_PM		0x00000800	/* Page mode		*/
#define CPU_BR_DRAM_FAC		0x00000600	/* First access timing	*/
#define CPU_BR_DRAM_BAC		0x00000180	/* Burst access timing	*/
#define CPU_BR_DRAM_PCC		0x00000040	/* Precharge cycles	*/
#define CPU_BR_DRAM_RAR		0x00000020	/* RAS active on refresh */
#define CPU_BR_DRAM_RR		0x0000001e	/* Refresh interval	*/

/*
*	Bank Register DRAM access value macros.
*
*	Maximum values are:
*
*		f <= 3		Wait states on first access of burst.
*		n <= 3		Wait states on subsequent accesses of burst.
*
*	Actual  timings  are  one,  two, or three SysClk cycles more;
*	consult the manual.
*/

#define CPU_BR_DRAM_ACCESS(f,n) (((f)<<9)|((n)<<7))

/*
*	Bank Register DRAM refresh value macro.
*
*	Maximum value is <= 15.
*/

#define CPU_BR_DRAM_REFRESH(n)  ((n)<<1)

/*
*	Bank Register High definitions.
*/

#define CPU_BRH_PCE		0x80000000	/* Parity check enable	*/

/*
*	Cache Debug Control Register definitions.
*/

#define CPU_CDBCR_CIS		0x00000010	/* Cache information select */
#define CPU_CDBCR_CSS		0x00000001	/* Cache side select	*/

/*
*	Debug Control Register definitions.
*/

#define CPU_DBCR_EDM		0x80000000	/* External debug mode	*/
#define CPU_DBCR_IDM		0x40000000	/* Internal debug mode	*/
#define CPU_DBCR_RST		0x30000000	/* Reset		*/
#define CPU_DBCR_IC			0x08000000	/* Instruction completion */
#define CPU_DBCR_BT			0x04000000	/* Branch taken		*/
#define CPU_DBCR_EDE		0x02000000	/* Exception		*/
#define CPU_DBCR_TDE		0x01000000	/* Trap			*/
#define CPU_DBCR_FER		0x00f80000	/* First events remaining */
#define CPU_DBCR_FT			0x00040000	/* Freeze timers	*/
#define CPU_DBCR_IA1		0x00020000	/* Inst address 1 enable */
#define CPU_DBCR_IA2		0x00010000	/* Inst address 2 enable */
#define CPU_DBCR_D1R		0x00008000	/* Data addr 1 read enable */
#define CPU_DBCR_D1W		0x00004000	/* Data addr 1 write enable */
#define CPU_DBCR_D1S		0x00003000	/* Data addr 1 size	*/
#define CPU_DBCR_D2R		0x00000800	/* Data addr 2 read enable */
#define CPU_DBCR_D2W		0x00000400	/* Data addr 2 write enable */
#define CPU_DBCR_D2S		0x00000300	/* Data addr 2 size	*/
#define CPU_DBCR_SBT		0x00000040	/* Second branch taken	*/
#define CPU_DBCR_SED		0x00000020	/* Second exception	*/
#define CPU_DBCR_STD		0x00000010	/* Second trap		*/
#define CPU_DBCR_SIA		0x00000008	/* Second IAC enable	*/
#define CPU_DBCR_SDA		0x00000004	/* Second DAC enable	*/
#define CPU_DBCR_JOI		0x00000002	/* JTAG outbound int enb */
#define CPU_DBCR_JII		0x00000001	/* JTAG inbound int enb	*/

/*
*	Debug Control Register reset field definitions.
*
*	Writing  one  of  these  patterns  to  the  DBCR will cause a
*	processor reset.
*/

#define CPU_DBCR_RST_CORE	0x10000000	/* Core reset		*/
#define CPU_DBCR_RST_CHIP	0x20000000	/* Chip reset		*/
#define CPU_DBCR_RST_SYSTEM	0x30000000	/* System reset		*/

/*
*	Debug Status Register definitions.
*
*	Bits  in  this  register are set to 1 by hardware, and may be
*	cleared by being written to 1 by software.
*/

#define CPU_DBSR_IC			0x80000000	/* Instruction completion */
#define CPU_DBSR_BT			0x40000000	/* Branch taken		*/
#define CPU_DBSR_EXC		0x20000000	/* Exception		*/
#define CPU_DBSR_TIE		0x10000000	/* Trap			*/
#define CPU_DBSR_UDE		0x08000000	/* Unconditional event	*/
#define CPU_DBSR_IA1		0x04000000	/* Inst address 1	*/
#define CPU_DBSR_IA2		0x02000000	/* Inst address 2	*/
#define CPU_DBSR_DR1		0x01000000	/* Data addr 1 read	*/
#define CPU_DBSR_DW1		0x00800000	/* Data addr 1 write	*/
#define CPU_DBSR_DR2		0x00400000	/* Data addr 2 read	*/
#define CPU_DBSR_DW2		0x00200000	/* Data addr 2 write	*/
#define CPU_DBSR_IDE		0x00100000	/* Imprecise event	*/

#define CPU_DBSR_MRR		0x00000300	/* Most recent reset	*/

#define CPU_DBSR_JIF		0x00000004	/* JTAG in buffer full	*/
#define CPU_DBSR_JIO		0x00000002	/* JTAG in buffer overrun */
#define CPU_DBSR_JOE		0x00000001	/* JTAG out buffer empty */

/*
*	DMA Channel Control Register definitions.
*/

#define CPU_DMACR_CE		0x80000000	/* Channel enable	*/
#define CPU_DMACR_CIE		0x40000000	/* Channel interrupt enable */
#define CPU_DMACR_TD		0x20000000	/* Transfer direction	*/
#define CPU_DMACR_PL		0x10000000	/* Peripheral location	*/
#define CPU_DMACR_PW		0x0c000000	/* Peripheral width	*/
#define CPU_DMACR_DAI		0x02000000	/* Dest addr increment	*/
#define CPU_DMACR_SAI		0x01000000	/* Source addr increment */
#define CPU_DMACR_CP		0x00800000	/* Channel priority	*/
#define CPU_DMACR_TM		0x00600000	/* Transfer mode	*/
#define CPU_DMACR_PSC		0x00180000	/* Peripheral setup cycles */
#define CPU_DMACR_PWC		0x0007e000	/* Peripheral wait cycles */
#define CPU_DMACR_PHC		0x00001c00	/* Peripheral hold cycles */
#define CPU_DMACR_ETD		0x00000200	/* EOT/TC pin direction	*/
#define CPU_DMACR_TCE		0x00000100	/* Terminal count enable */
#define CPU_DMACR_CH		0x00000080	/* Chaining enable	*/
#define CPU_DMACR_BME		0x00000040	/* Burst mode enable	*/
#define CPU_DMACR_ECE		0x00000020	/* EOT chain mode enable */
#define CPU_DMACR_TCD		0x00000010	/* TC chain mode disable */
#define CPU_DMACR_PCE		0x00000008	/* Parity check enable	*/

/*
*	DMA Channel Control Register peripheral width definitions.
*/

#define CPU_DMACR_PW_8		0x00000000	/* 8 bit peripheral	*/
#define CPU_DMACR_PW_16		0x04000000	/* 16 bit peripheral	*/
#define CPU_DMACR_PW_32		0x08000000	/* 32 bit peripheral	*/
#define CPU_DMACR_PW_MEM	0x0c000000	/* Memory-to-memory	*/

/*
*	DMA Channel Control Register transfer mode definitions.
*/

#define CPU_DMACR_TM_BUFFERED	0x00000000	/* Buffered mode	*/
#define CPU_DMACR_TM_FLYBY		0x00200000	/* Fly-by mode		*/
#define CPU_DMACR_TM_MEM_SW		0x00400000	/* SW initiated mem-to-mem */
#define CPU_DMACR_TM_MEM_HW		0x00600000	/* HW initiated mem-to-mem */

/*
*	DMA Channel Control Register peripheral timing definitions.
*
*	Maximum values are:
*
*		s <= 3		Peripheral setup cycles.
*		w <= 63		Peripheral wait cycles.
*		h <= 7		Peripheral hold cycles.
*/

#define CPU_DMACR_TIMING(s,w,h) (((s)<<19)|((w)<<13)|((h)<<10))

/*
*	DMA Status Register definitions.
*
*	Bits  in  this  register are set to 1 by hardware, and may be
*	cleared by being written to 1 by software.
*/

#define CPU_DMASR_CS0		0x80000000	/* Channel 0 TC reached	*/
#define CPU_DMASR_CS1		0x40000000	/* Channel 1 TC reached	*/
#define CPU_DMASR_CS2		0x20000000	/* Channel 2 TC reached	*/
#define CPU_DMASR_CS3		0x10000000	/* Channel 3 TC reached	*/

#define CPU_DMASR_TS0		0x08000000	/* Channel 0 EOT requested */
#define CPU_DMASR_TS1		0x04000000	/* Channel 1 EOT requested */
#define CPU_DMASR_TS2		0x02000000	/* Channel 2 EOT requested */
#define CPU_DMASR_TS3		0x01000000	/* Channel 3 EOT requested */

#define CPU_DMASR_RI0		0x00800000	/* Channel 0 error status */
#define CPU_DMASR_RI1		0x00400000	/* Channel 1 error status */
#define CPU_DMASR_RI2		0x00200000	/* Channel 2 error status */
#define CPU_DMASR_RI3		0x00100000	/* Channel 3 error status */

#define CPU_DMASR_CT0		0x00080000	/* Channel 0 chained	*/

#define CPU_DMASR_IR0		0x00040000	/* Chan 0 int DMA pending */
#define CPU_DMASR_IR1		0x00020000	/* Chan 1 int DMA pending */
#define CPU_DMASR_IR2		0x00010000	/* Chan 2 int DMA pending */
#define CPU_DMASR_IR3		0x00008000	/* Chan 3 int DMA pending */

#define CPU_DMASR_ER0		0x00004000	/* Chan 0 ext DMA pending */
#define CPU_DMASR_ER1		0x00002000	/* Chan 1 ext DMA pending */
#define CPU_DMASR_ER2		0x00001000	/* Chan 2 ext DMA pending */
#define CPU_DMASR_ER3		0x00000800	/* Chan 3 ext DMA pending */

#define CPU_DMASR_CB0		0x00000400	/* Channel 0 busy	*/
#define CPU_DMASR_CB1		0x00000200	/* Channel 1 busy	*/
#define CPU_DMASR_CB2		0x00000100	/* Channel 2 busy	*/
#define CPU_DMASR_CB3		0x00000080	/* Channel 3 busy	*/

#define CPU_DMASR_CT1		0x00000040	/* Channel 1 chained	*/
#define CPU_DMASR_CT2		0x00000020	/* Channel 2 chained	*/
#define CPU_DMASR_CT3		0x00000010	/* Channel 3 chained	*/

/*
*	Exception Syndrome Register definitions.
*/

#define CPU_ESR_IMCP		0x80000000	/* Protection violation	*/
#define CPU_ESR_IMCN		0x40000000	/* Non-configured access */
#define CPU_ESR_IMCB		0x20000000	/* Bus error		*/
#define CPU_ESR_IMCT		0x10000000	/* Bus timeout		*/
#define CPU_ESR_PIL			0x08000000	/* Illegal instruction	*/
#define CPU_ESR_PPR			0x04000000	/* Privilege violation	*/
#define CPU_ESR_PTR			0x02000000	/* Program trap		*/
#define CPU_ESR_DST			0x00800000	/* Data store operation	*/
#define CPU_ESR_DIZ			0x00400000	/* Zone fault		*/

/*
*	External Interrupt Enable Register definitions.
*/

#define CPU_EXIER_CIE		0x80000000	/* Critical interrupt	*/
#define CPU_EXIER_SRIE		0x08000000	/* Serial port receive	*/
#define CPU_EXIER_STIE		0x04000000	/* Serial port transmit	*/
#define CPU_EXIER_JRIE		0x02000000	/* JTAG port receive	*/
#define CPU_EXIER_JTIE		0x01000000	/* JTAG port transmit	*/
#define CPU_EXIER_D0IE		0x00800000	/* DMA chan 0 interrupt	*/
#define CPU_EXIER_D1IE		0x00400000	/* DMA chan 1 interrupt	*/
#define CPU_EXIER_D2IE		0x00200000	/* DMA chan 2 interrupt	*/
#define CPU_EXIER_D3IE		0x00100000	/* DMA chan 3 interrupt	*/

#define CPU_EXIER_E0IE		0x00000010	/* External interrupt 0	*/
#define CPU_EXIER_E1IE		0x00000008	/* External interrupt 1	*/
#define CPU_EXIER_E2IE		0x00000004	/* External interrupt 2	*/
#define CPU_EXIER_E3IE		0x00000002	/* External interrupt 3	*/
#define CPU_EXIER_E4IE		0x00000001	/* External interrupt 4	*/

/*
*	External Interrupt Status Register definitions.
*
*	Bits  in  this  register are set to 1 by hardware, and may be