cpu_403.h

umon bootloader source code, support mips cpu.

/*
 * %W% %E%
 *
 * Copyright (c) 1998-1999 Lucent Technologies, Inc.  All Rights Reserved.
 *
 * This software is the confidential and proprietary information of Lucent
 * Technologies, Inc. ("Confidential Information").  You shall not disclose
 * such Confidential Information and shall use it only in accordance with
 * the terms of the license agreement you entered into with Lucent.
 *
 * LUCENT TECHNOLOGIES MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
 * SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
 * NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
 * A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  LUCENT TECHNOLOGIES SHALL
 * NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING,
 * MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
 */

/*******************************************************************************
*
*	cpu403.h
*
*	CPU definitions for the Power PC PPC403GCX.
*
*	May 1998	S. McCaskill
*	Mar 1999	R. Snyder		Add cpu.s functions as asm macros
*	May 1999	R. Snyder		Add more serial port definitions
*
*	This file includes rewrites of some of the functions from Scott McCaskill's
*	cpu.s file.  See cpu403.c for the others.  It implements functions to
*	access the PowerPC's special purpose and device control registers.  The
*	Diab/Data assembler does not support a "repeat" directive, so Scott's
*	cpu.s file could not be assembled.
*
*	The following functions are provided:
*
*		value = CPU_Read_SPR(index)
*		value = CPU_Read_DCR(index)
*
*	return the value of the register whose index is specified.
*
*		CPU_Write_SPR(index,value)
*		CPU_Write_DCR(index,value)
*
*	write a value into the register whose index is specified.
*
*	WARNING, unlike Scott's routines, reading from a non-existent register or
*	writing to a non-existent register have undefined/undesired effects.
*
*	For  additional  information,  consult chapter 12 of the "IBM
*	PPC403GCX Embedded Controller User's Manual".
*
*******************************************************************************/
#ifndef CPU403_H
#define CPU403_H

/*
*	Declare access functions in cpu.s
*/

#if 0
asm unsigned long   CPU_Read_SPR(unsigned int reg)
{
% con reg
    mfspr   r3, reg
}

asm void	    CPU_Write_SPR(unsigned int reg, unsigned long value)
{
% con reg; reg value
    mtspr   reg, value
}

asm unsigned long   CPU_Read_DCR(unsigned int reg)
{
% con reg
    mfdcr   r3, reg
}

asm void	    CPU_Write_DCR(unsigned int reg, unsigned long value)
{
% con reg; reg value
    mtdcr   reg, value
}

asm unsigned long   CPU_Read_MSR()
{
    mfmsr   r3
}

asm void	    CPU_Write_MSR(unsigned long value)
{
% reg value
    mtmsr   r3
}

extern void		CPU_Read_TB(unsigned long *pTimeBase);
extern void		CPU_uwait(unsigned long uSecs);
extern unsigned long	CPU_usec_Ticks();
#endif

/*
*	Special Purpose Registers.
*/

#define CPU_SPR_XER			0x001	/* Fixed point exception register */

#define CPU_SPR_LR			0x008	/* Link register		*/
#define CPU_SPR_CTR			0x009	/* Count register		*/

#define CPU_SPR_SRR0		0x01a	/* Save/restore register 0	*/
#define CPU_SPR_SRR1		0x01b	/* Save/restore register 1	*/

#define CPU_SPR_SPRG0		0x110	/* Special general register 0	*/
#define CPU_SPR_SPRG1		0x111	/* Special general register 1	*/
#define CPU_SPR_SPRG2		0x112	/* Special general register 2	*/
#define CPU_SPR_SPRG3		0x113	/* Special general register 3	*/

#define CPU_SPR_PVR			0x11f	/* Processor version register	*/

#define CPU_SPR_ZPR			0x3b0	/* Zone protection register	*/
#define CPU_SPR_PID			0x3b1	/* Process ID			*/
#define CPU_SPR_SGR			0x3b9	/* Storage guarded register	*/
#define CPU_SPR_DCWR		0x3ba	/* Data cache write-through register */

#define CPU_SPR_TBHU		0x3cc	/* Time base high user-mode	*/
#define CPU_SPR_TBLU		0x3cd	/* Time base low user-mode	*/

#define CPU_SPR_ICDBDR		0x3d3	/* Inst cache debug data register */
#define CPU_SPR_ESR			0x3d4	/* Exception syndrome register	*/
#define CPU_SPR_DEAR		0x3d5	/* Data error address register	*/
#define CPU_SPR_EVPR		0x3d6	/* Exception vector prefix register */
#define CPU_SPR_CDBCR		0x3d7	/* Cache debug control register	*/
#define CPU_SPR_TSR			0x3d8	/* Timer status register	*/

#define CPU_SPR_TCR			0x3da	/* Timer control register	*/
#define CPU_SPR_PIT			0x3db	/* Programmable interval timer	*/
#define CPU_SPR_TBHI		0x3dc	/* Time base high		*/
#define CPU_SPR_TBLO		0x3dd	/* Time base low		*/
#define CPU_SPR_SRR2		0x3de	/* Save/restore register 2	*/
#define CPU_SPR_SRR3		0x3df	/* Save/restore register 3	*/

#define CPU_SPR_DBSR		0x3f0	/* Debug status register	*/
#define CPU_SPR_DBCR		0x3f2	/* Debug control register	*/
#define CPU_SPR_IAC1		0x3f4	/* Instruction address compare 1 */
#define CPU_SPR_IAC2		0x3f5	/* Instruction address compare 2 */
#define CPU_SPR_DAC1		0x3f6	/* Data address compare 1	*/
#define CPU_SPR_DAC2		0x3f7	/* Data address compare 2	*/

#define CPU_SPR_DCCR		0x3fa	/* Data cache cacheability register */
#define CPU_SPR_ICCR		0x3fb	/* Inst cache cacheability register */
#define CPU_SPR_PBL1		0x3fc	/* Protection bound lower 1	*/
#define CPU_SPR_PBU1		0x3fd	/* Protection bound upper 1	*/
#define CPU_SPR_PBL2		0x3fe	/* Protection bound lower 2	*/
#define CPU_SPR_PBU2		0x3ff	/* Protection bound upper 2	*/

/*
*	Device Control Registers.
*/

#define CPU_DCR_EXISR		0x040	/* External interrupt status register */
#define CPU_DCR_EXIER		0x042	/* External interrupt enable register */

#define CPU_DCR_BRH0		0x070	/* Bank register high 0		*/
#define CPU_DCR_BRH1		0x071	/* Bank register high 1		*/
#define CPU_DCR_BRH2		0x072	/* Bank register high 2		*/
#define CPU_DCR_BRH3		0x073	/* Bank register high 3		*/
#define CPU_DCR_BRH4		0x074	/* Bank register high 4		*/
#define CPU_DCR_BRH5		0x075	/* Bank register high 5		*/
#define CPU_DCR_BRH6		0x076	/* Bank register high 6		*/
#define CPU_DCR_BRH7		0x077	/* Bank register high 7		*/

#define CPU_DCR_BR0			0x080	/* Bank register 0		*/
#define CPU_DCR_BR1			0x081	/* Bank register 1		*/
#define CPU_DCR_BR2			0x082	/* Bank register 2		*/
#define CPU_DCR_BR3			0x083	/* Bank register 3		*/
#define CPU_DCR_BR4			0x084	/* Bank register 4		*/
#define CPU_DCR_BR5			0x085	/* Bank register 5		*/
#define CPU_DCR_BR6			0x086	/* Bank register 6		*/
#define CPU_DCR_BR7			0x087	/* Bank register 7		*/

#define CPU_DCR_BEAR		0x090	/* Bus error address register	*/
#define CPU_DCR_BESR		0x091	/* Bus error syndrome register	*/

#define CPU_DCR_IOCR		0x0a0	/* I/O configuration register	*/

#define CPU_DCR_DMACR0		0x0c0	/* DMA channel control register 0 */
#define CPU_DCR_DMACT0		0x0c1	/* DMA count register 0		*/
#define CPU_DCR_DMADA0		0x0c2	/* DMA destination address register 0 */
#define CPU_DCR_DMASA0		0x0c3	/* DMA source address register 0 */
#define CPU_DCR_DMACC0		0x0c4	/* DMA chained count 0		*/

#define CPU_DCR_DMACR1		0x0c8	/* DMA channel control register 1 */
#define CPU_DCR_DMACT1		0x0c9	/* DMA count register 1		*/
#define CPU_DCR_DMADA1		0x0ca	/* DMA destination address register 1 */
#define CPU_DCR_DMASA1		0x0cb	/* DMA source address register 1 */
#define CPU_DCR_DMACC1		0x0cc	/* DMA chained count 1		*/

#define CPU_DCR_DMACR2		0x0d0	/* DMA channel control register 2 */
#define CPU_DCR_DMACT2		0x0d1	/* DMA count register 2		*/
#define CPU_DCR_DMADA2		0x0d2	/* DMA destination address register 2 */
#define CPU_DCR_DMASA2		0x0d3	/* DMA source address register 2 */
#define CPU_DCR_DMACC2		0x0d4	/* DMA chained count 2		*/

#define CPU_DCR_DMACR3		0x0d8	/* DMA channel control register 3 */
#define CPU_DCR_DMACT3		0x0d9	/* DMA count register 3		*/
#define CPU_DCR_DMADA3		0x0da	/* DMA destination address register 3 */
#define CPU_DCR_DMASA3		0x0db	/* DMA source address register 3 */
#define CPU_DCR_DMACC3		0x0dc	/* DMA chained count 3		*/

#define CPU_DCR_DMASR		0x0e0	/* DMA status register		*/

/*
*	BESR definitions.
*/

#define CPU_BESR_DSES			0x80000000	/* Data-side error	*/
#define CPU_BESR_DMES			0x40000000	/* DMA operation error	*/
#define CPU_BESR_RWS			0x20000000	/* Read/write status	*/
#define CPU_BESR_ET				0x1c000000	/* Error type mask	*/

#define CPU_BESR_ET_PROT		0x00000000	/* Protection violation	*/
#define CPU_BESR_ET_PARITY		0x04000000	/* Parity error		*/
#define CPU_BESR_ET_NOTCONFIG	0x08000000	/* Access not configured */
#define CPU_BESR_ET_BUS			0x10000000	/* Bus error		*/
#define CPU_BESR_ET_TIMEOUT		0x18000000	/* Bus timeout		*/

/*
*	Bank Register common definitions.
*
*	Note  that  only  BR4..BR7 may be used for DRAM. BR0..BR3 are
*	hard-wired  for  SRAM;  their CPU_BR_SD bits are ignored when
*	written, and return zero when read.
*/

#define CPU_BR_BAS			0xff000000	/* Base address of bank	*/
#define CPU_BR_BS			0x00e00000	/* Bank size		*/
#define CPU_BR_BU_WRITE		0x00100000	/* Bank is writeable	*/
#define CPU_BR_BU_READ		0x00080000	/* Bank is readable	*/
#define CPU_BR_SLF			0x00040000	/* Sequential line fill	*/
#define CPU_BR_BW			0x00018000	/* Bus width		*/
#define CPU_BR_SD			0x00000001	/* Set for SRAM		*/

#define CPU_BR_BASE_ADDR(n) (((n)&0x0ff00000)<<4) /* Macro to set base addr */

/*
*	Bank Register bank size definitions.
*/

#define CPU_BR_BS_1MB		0x00000000
#define CPU_BR_BS_2MB		0x00200000
#define CPU_BR_BS_4MB		0x00400000
#define CPU_BR_BS_8MB		0x00600000
#define CPU_BR_BS_16MB		0x00800000
#define CPU_BR_BS_32MB		0x00a00000
#define CPU_BR_BS_64MB		0x00c00000

/*
*	Bank Register bus width definitions.
*/

#define CPU_BR_BW_8			0x00000000	/* 8-bit bus		*/
#define CPU_BR_BW_16		0x00008000	/* 16-bit bus		*/
#define CPU_BR_BW_32		0x00010000	/* 32-bit bus		*/

/*
*	Bank Register SRAM definitions.
*/

#define CPU_BR_SRAM_SLF		0x00040000	/* Sequential line fill */
#define CPU_BR_SRAM_BME		0x00020000	/* Burst mode enable	*/
#define CPU_BR_SRAM_RE		0x00004000	/* Ready enable		*/
#define CPU_BR_SRAM_TWT		0x00003f00	/* Transfer wait	*/
#define CPU_BR_SRAM_CSN		0x00000080	/* Chip select timing	*/
#define CPU_BR_SRAM_OEN		0x00000040	/* Output enable timing	*/