gt64240.h

umon bootloader source code, support mips cpu.

#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS			0x998
#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS			0x99c
#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a0
#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a4
#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a8
#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8ac
#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a0
#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a4
#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a8
#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9ac
#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b0
#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b4
#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b8
#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8bc
#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b0
#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b4
#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b8
#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9bc

/*
 * DMA Channel Control
 */

#define CHANNEL0CONTROL						0x840
#define CHANNEL0CONTROL_HIGH					0x880

#define CHANNEL1CONTROL						0x844
#define CHANNEL1CONTROL_HIGH					0x884

#define CHANNEL2CONTROL						0x848
#define CHANNEL2CONTROL_HIGH					0x888

#define CHANNEL3CONTROL						0x84C
#define CHANNEL3CONTROL_HIGH					0x88C

#define CHANNEL4CONTROL						0x940
#define CHANNEL4CONTROL_HIGH					0x980

#define CHANNEL5CONTROL						0x944
#define CHANNEL5CONTROL_HIGH					0x984

#define CHANNEL6CONTROL						0x948
#define CHANNEL6CONTROL_HIGH					0x988

#define CHANNEL7CONTROL						0x94C
#define CHANNEL7CONTROL_HIGH					0x98C


/*
 * DMA Arbiter
 */

#define ARBITER_CONTROL_0_3					0x860
#define ARBITER_CONTROL_4_7					0x960


/*
 * DMA Interrupt
 */

#define CHANELS0_3_INTERRUPT_CAUSE				0x8c0
#define CHANELS0_3_INTERRUPT_MASK				0x8c4
#define CHANELS0_3_ERROR_ADDRESS				0x8c8
#define CHANELS0_3_ERROR_SELECT					0x8cc
#define CHANELS4_7_INTERRUPT_CAUSE				0x9c0
#define CHANELS4_7_INTERRUPT_MASK				0x9c4
#define CHANELS4_7_ERROR_ADDRESS				0x9c8
#define CHANELS4_7_ERROR_SELECT					0x9cc


/*
 * DMA Debug (for internal use)
 */

#define DMA_X0_ADDRESS						0x8e0
#define DMA_X0_COMMAND_AND_ID					0x8e4
#define DMA_X0_WRITE_DATA_LOW					0x8e8
#define DMA_X0_WRITE_DATA_HIGH					0x8ec
#define DMA_X0_WRITE_BYTE_ENABLE				0x8f8
#define DMA_X0_READ_DATA_LOW					0x8f0
#define DMA_X0_READ_DATA_HIGH					0x8f4
#define DMA_X0_READ_ID						0x8fc
#define DMA_X1_ADDRESS						0x9e0
#define DMA_X1_COMMAND_AND_ID					0x9e4
#define DMA_X1_WRITE_DATA_LOW					0x9e8
#define DMA_X1_WRITE_DATA_HIGH					0x9ec
#define DMA_X1_WRITE_BYTE_ENABLE				0x9f8
#define DMA_X1_READ_DATA_LOW					0x9f0
#define DMA_X1_READ_DATA_HIGH					0x9f4
#define DMA_X1_READ_ID						0x9fc

/*
 * Timer_Counter
 */

#define TIMER_COUNTER0						0x850
#define TIMER_COUNTER1						0x854
#define TIMER_COUNTER2						0x858
#define TIMER_COUNTER3						0x85C
#define TIMER_COUNTER_0_3_CONTROL				0x864
#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE			0x868
#define TIMER_COUNTER_0_3_INTERRUPT_MASK			0x86c
#define TIMER_COUNTER4						0x950
#define TIMER_COUNTER5						0x954
#define TIMER_COUNTER6						0x958
#define TIMER_COUNTER7						0x95C
#define TIMER_COUNTER_4_7_CONTROL				0x964
#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE			0x968
#define TIMER_COUNTER_4_7_INTERRUPT_MASK			0x96c

/*
 * PCI Slave Address Decoding
 */

#define PCI_0SCS_0_BANK_SIZE					0xc08
#define PCI_1SCS_0_BANK_SIZE					0xc88
#define PCI_0SCS_1_BANK_SIZE					0xd08
#define PCI_1SCS_1_BANK_SIZE					0xd88
#define PCI_0SCS_2_BANK_SIZE					0xc0c
#define PCI_1SCS_2_BANK_SIZE					0xc8c
#define PCI_0SCS_3_BANK_SIZE					0xd0c
#define PCI_1SCS_3_BANK_SIZE					0xd8c
#define PCI_0CS_0_BANK_SIZE					0xc10
#define PCI_1CS_0_BANK_SIZE					0xc90
#define PCI_0CS_1_BANK_SIZE					0xd10
#define PCI_1CS_1_BANK_SIZE					0xd90
#define PCI_0CS_2_BANK_SIZE					0xd18
#define PCI_1CS_2_BANK_SIZE					0xd98
#define PCI_0CS_3_BANK_SIZE					0xc14
#define PCI_1CS_3_BANK_SIZE					0xc94
#define PCI_0CS_BOOT_BANK_SIZE					0xd14
#define PCI_1CS_BOOT_BANK_SIZE					0xd94
#define PCI_0P2P_MEM0_BAR_SIZE					0xd1c
#define PCI_1P2P_MEM0_BAR_SIZE					0xd9c
#define PCI_0P2P_MEM1_BAR_SIZE					0xd20
#define PCI_1P2P_MEM1_BAR_SIZE					0xda0
#define PCI_0P2P_I_O_BAR_SIZE					0xd24
#define PCI_1P2P_I_O_BAR_SIZE					0xda4
#define PCI_0CPU_BAR_SIZE					0xd28
#define PCI_1CPU_BAR_SIZE					0xda8
#define PCI_0DAC_SCS_0_BANK_SIZE				0xe00
#define PCI_1DAC_SCS_0_BANK_SIZE				0xe80
#define PCI_0DAC_SCS_1_BANK_SIZE				0xe04
#define PCI_1DAC_SCS_1_BANK_SIZE				0xe84
#define PCI_0DAC_SCS_2_BANK_SIZE				0xe08
#define PCI_1DAC_SCS_2_BANK_SIZE				0xe88
#define PCI_0DAC_SCS_3_BANK_SIZE				0xe0c
#define PCI_1DAC_SCS_3_BANK_SIZE				0xe8c
#define PCI_0DAC_CS_0_BANK_SIZE					0xe10
#define PCI_1DAC_CS_0_BANK_SIZE					0xe90
#define PCI_0DAC_CS_1_BANK_SIZE					0xe14
#define PCI_1DAC_CS_1_BANK_SIZE					0xe94
#define PCI_0DAC_CS_2_BANK_SIZE					0xe18
#define PCI_1DAC_CS_2_BANK_SIZE					0xe98
#define PCI_0DAC_CS_3_BANK_SIZE					0xe1c
#define PCI_1DAC_CS_3_BANK_SIZE					0xe9c
#define PCI_0DAC_BOOTCS_BANK_SIZE				0xe20
#define PCI_1DAC_BOOTCS_BANK_SIZE				0xea0
#define PCI_0DAC_P2P_MEM0_BAR_SIZE				0xe24
#define PCI_1DAC_P2P_MEM0_BAR_SIZE				0xea4
#define PCI_0DAC_P2P_MEM1_BAR_SIZE				0xe28
#define PCI_1DAC_P2P_MEM1_BAR_SIZE				0xea8
#define PCI_0DAC_CPU_BAR_SIZE					0xe2c
#define PCI_1DAC_CPU_BAR_SIZE					0xeac
#define PCI_0EXPANSION_ROM_BAR_SIZE				0xd2c
#define PCI_1EXPANSION_ROM_BAR_SIZE				0xdac
#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE			0xc3c
#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE			0xcbc
#define PCI_0SCS_0_BASE_ADDRESS_REMAP				0xc48
#define PCI_1SCS_0_BASE_ADDRESS_REMAP				0xcc8
#define PCI_0SCS_1_BASE_ADDRESS_REMAP				0xd48
#define PCI_1SCS_1_BASE_ADDRESS_REMAP				0xdc8
#define PCI_0SCS_2_BASE_ADDRESS_REMAP				0xc4c
#define PCI_1SCS_2_BASE_ADDRESS_REMAP				0xccc
#define PCI_0SCS_3_BASE_ADDRESS_REMAP				0xd4c
#define PCI_1SCS_3_BASE_ADDRESS_REMAP				0xdcc
#define PCI_0CS_0_BASE_ADDRESS_REMAP				0xc50
#define PCI_1CS_0_BASE_ADDRESS_REMAP				0xcd0
#define PCI_0CS_1_BASE_ADDRESS_REMAP				0xd50
#define PCI_1CS_1_BASE_ADDRESS_REMAP				0xdd0
#define PCI_0CS_2_BASE_ADDRESS_REMAP				0xd58
#define PCI_1CS_2_BASE_ADDRESS_REMAP				0xdd8
#define PCI_0CS_3_BASE_ADDRESS_REMAP				0xc54
#define PCI_1CS_3_BASE_ADDRESS_REMAP				0xcd4
#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP			0xd54
#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP			0xdd4
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xd5c
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xddc
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH			0xd60
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH			0xde0
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW			0xd64
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW			0xde4
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH			0xd68
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH			0xde8
#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP				0xd6c
#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP				0xdec
#define PCI_0CPU_BASE_ADDRESS_REMAP				0xd70
#define PCI_1CPU_BASE_ADDRESS_REMAP				0xdf0
#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP			0xf00
#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP			0xff0
#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP			0xf04
#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP			0xf84
#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP			0xf08
#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP			0xf88
#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP			0xf0c
#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP			0xf8c
#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP			0xf10
#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP			0xf90
#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP			0xf14
#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP			0xf94
#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP			0xf18
#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP			0xf98
#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP			0xf1c
#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP			0xf9c
#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP			0xf20
#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP			0xfa0
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xf24
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xfa4
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xf28
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xfa8
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xf2c
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xfac
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xf30
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xfb0
#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP				0xf34
#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP				0xfb4
#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP			0xf38
#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP			0xfb8
#define PCI_0ADDRESS_DECODE_CONTROL				0xd3c
#define PCI_1ADDRESS_DECODE_CONTROL				0xdbc

/*
 * PCI Control
 */

#define PCI_0COMMAND						0xc00
#define PCI_1COMMAND						0xc80
#define PCI_0MODE						0xd00
#define PCI_1MODE						0xd80
#define PCI_0TIMEOUT_RETRY					0xc04
#define PCI_1TIMEOUT_RETRY					0xc84
#define PCI_0READ_BUFFER_DISCARD_TIMER				0xd04
#define PCI_1READ_BUFFER_DISCARD_TIMER				0xd84
#define MSI_0TRIGGER_TIMER					0xc38
#define MSI_1TRIGGER_TIMER					0xcb8
#define PCI_0ARBITER_CONTROL					0x1d00
#define PCI_1ARBITER_CONTROL					0x1d80
/* changing untill here */
#define PCI_0CROSS_BAR_CONTROL_LOW				 0x1d08
#define PCI_0CROSS_BAR_CONTROL_HIGH				 0x1d0c
#define PCI_0CROSS_BAR_TIMEOUT					 0x1d04
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW		 0x1d18
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH		 0x1d1c
#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER			 0x1d10
#define PCI_0P2P_CONFIGURATION					 0x1d14
#define PCI_0ACCESS_CONTROL_BASE_0_LOW				 0x1e00
#define PCI_0ACCESS_CONTROL_BASE_0_HIGH				 0x1e04
#define PCI_0ACCESS_CONTROL_TOP_0				 0x1e08
#define PCI_0ACCESS_CONTROL_BASE_1_LOW				 0c1e10
#define PCI_0ACCESS_CONTROL_BASE_1_HIGH				 0x1e14
#define PCI_0ACCESS_CONTROL_TOP_1				 0x1e18
#define PCI_0ACCESS_CONTROL_BASE_2_LOW				 0c1e20
#define PCI_0ACCESS_CONTROL_BASE_2_HIGH				 0x1e24
#define PCI_0ACCESS_CONTROL_TOP_2				 0x1e28
#define PCI_0ACCESS_CONTROL_BASE_3_LOW				 0c1e30
#define PCI_0ACCESS_CONTROL_BASE_3_HIGH				 0x1e34
#define PCI_0ACCESS_CONTROL_TOP_3				 0x1e38
#define PCI_0ACCESS_CONTROL_BASE_4_LOW				 0c1e40
#define PCI_0ACCESS_CONTROL_BASE_4_HIGH				 0x1e44
#define PCI_0ACCESS_CONTROL_TOP_4				 0x1e48
#define PCI_0ACCESS_CONTROL_BASE_5_LOW				 0c1e50
#define PCI_0ACCESS_CONTROL_BASE_5_HIGH				 0x1e54
#define PCI_0ACCESS_CONTROL_TOP_5				 0x1e58
#define PCI_0ACCESS_CONTROL_BASE_6_LOW				 0c1e60
#define PCI_0ACCESS_CONTROL_BASE_6_HIGH				 0x1e64
#define PCI_0ACCESS_CONTROL_TOP_6				 0x1e68
#define PCI_0ACCESS_CONTROL_BASE_7_LOW				 0c1e70
#define PCI_0ACCESS_CONTROL_BASE_7_HIGH				 0x1e74
#define PCI_0ACCESS_CONTROL_TOP_7				 0x1e78
#define PCI_1CROSS_BAR_CONTROL_LOW				 0x1d88
#define PCI_1CROSS_BAR_CONTROL_HIGH				 0x1d8c
#define PCI_1CROSS_BAR_TIMEOUT					 0x1d84
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW		 0x1d98
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH		 0x1d9c
#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER			 0x1d90
#define PCI_1P2P_CONFIGURATION					 0x1d94
#define PCI_1ACCESS_CONTROL_BASE_0_LOW				 0x1e80
#define PCI_1ACCESS_CONTROL_BASE_0_HIGH				 0x1e84
#define PCI_1ACCESS_CONTROL_TOP_0				 0x1e88
#define PCI_1ACCESS_CONTROL_BASE_1_LOW				 0c1e90
#define PCI_1ACCESS_CONTROL_BASE_1_HIGH				 0x1e94
#define PCI_1ACCESS_CONTROL_TOP_1				 0x1e98
#define PCI_1ACCESS_CONTROL_BASE_2_LOW				 0c1ea0
#define PCI_1ACCESS_CONTROL_BASE_2_HIGH				 0x1ea4
#define PCI_1ACCESS_CONTROL_TOP_2				 0x1ea8
#define PCI_1ACCESS_CONTROL_BASE_3_LOW				 0c1eb0
#define PCI_1ACCESS_CONTROL_BASE_3_HIGH				 0x1eb4
#define PCI_1ACCESS_CONTROL_TOP_3				 0x1eb8
#define PCI_1ACCESS_CONTROL_BASE_4_LOW				 0c1ec0
#define PCI_1ACCESS_CONTROL_BASE_4_HIGH				 0x1ec4
#define PCI_1ACCESS_CONTROL_TOP_4				 0x1ec8
#define PCI_1ACCESS_CONTROL_BASE_5_LOW				 0c1ed0
#define PCI_1ACCESS_CONTROL_BASE_5_HIGH				 0x1ed4
#define PCI_1ACCESS_CONTROL_TOP_5				 0x1ed8
#define PCI_1ACCESS_CONTROL_BASE_6_LOW				 0c1ee0
#define PCI_1ACCESS_CONTROL_BASE_6_HIGH				 0x1ee4
#define PCI_1ACCESS_CONTROL_TOP_6				 0x1ee8
#define PCI_1ACCESS_CONTROL_BASE_7_LOW				 0c1ef0
#define PCI_1ACCESS_CONTROL_BASE_7_HIGH				 0x1ef4