mipsregs.h

umon bootloader source code, support mips cpu.

#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
#define write_c0_framemask(val)	__write_32bit_c0_register($21, 0, val)

/* RM9000 PerfControl performance counter control register */
#define read_c0_perfcontrol()	__read_32bit_c0_register($22, 0)
#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)

#define read_c0_diag()		__read_32bit_c0_register($22, 0)
#define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)

#define read_c0_diag1()		__read_32bit_c0_register($22, 1)
#define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)

#define read_c0_diag2()		__read_32bit_c0_register($22, 2)
#define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)

#define read_c0_diag3()		__read_32bit_c0_register($22, 3)
#define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)

#define read_c0_diag4()		__read_32bit_c0_register($22, 4)
#define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)

#define read_c0_diag5()		__read_32bit_c0_register($22, 5)
#define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)

#define read_c0_debug()		__read_32bit_c0_register($23, 0)
#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)

#define read_c0_depc()		__read_ulong_c0_register($24, 0)
#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)

/*
 * MIPS32 / MIPS64 performance counters
 */
#define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
#define write_c0_perfctrl0(val)	__write_32bit_c0_register($25, 0, val)
#define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
#define write_c0_perfcntr0(val)	__write_32bit_c0_register($25, 1, val)
#define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
#define write_c0_perfctrl1(val)	__write_32bit_c0_register($25, 2, val)
#define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
#define write_c0_perfcntr1(val)	__write_32bit_c0_register($25, 3, val)
#define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
#define write_c0_perfctrl2(val)	__write_32bit_c0_register($25, 4, val)
#define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
#define write_c0_perfcntr2(val)	__write_32bit_c0_register($25, 5, val)
#define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
#define write_c0_perfctrl3(val)	__write_32bit_c0_register($25, 6, val)
#define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
#define write_c0_perfcntr3(val)	__write_32bit_c0_register($25, 7, val)

/* RM9000 PerfCount performance counter register */
#define read_c0_perfcount()	__read_64bit_c0_register($25, 0)
#define write_c0_perfcount(val)	__write_64bit_c0_register($25, 0, val)

#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)

#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
#define write_c0_derraddr0(val)	__write_ulong_c0_register($26, 1, val)

#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)

#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
#define write_c0_derraddr1(val)	__write_ulong_c0_register($27, 1, val)

#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)

#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)

#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)

/*
 * Macros to access the floating point coprocessor control registers
 */
#define read_32bit_cp1_register(source)                         \
({ int __res;                                                   \
	__asm__ __volatile__(                                   \
	".set\tpush\n\t"					\
	".set\treorder\n\t"					\
        "cfc1\t%0,"STR(source)"\n\t"                            \
	".set\tpop"						\
        : "=r" (__res));                                        \
        __res;})

#define rddsp(mask)							\
({									\
	unsigned int __res;						\
									\
	__asm__ __volatile__(						\
	"	.set	push				\n"		\
	"	.set	noat				\n"		\
	"	# rddsp $1, %x1				\n"		\
	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
	"	move	%0, $1				\n"		\
	"	.set	pop				\n"		\
	: "=r" (__res)							\
	: "i" (mask));							\
	__res;								\
})

#define wrdsp(val, mask)						\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# wrdsp $1, %x1					\n"	\
	"	.word	0x7c2004f8 | (%x1 << 15)		\n"	\
	"	.set	pop					\n"	\
        :								\
	: "r" (val), "i" (mask));					\
} while (0)

#if 0	/* Need DSP ASE capable assembler ... */
#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})

#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})

#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))

#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))

#else

#define mfhi0()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mfhi	%0, $ac0		\n"			\
	"	.word	0x00000810		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mfhi1()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mfhi	%0, $ac1		\n"			\
	"	.word	0x00200810		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mfhi2()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mfhi	%0, $ac2		\n"			\
	"	.word	0x00400810		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mfhi3()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mfhi	%0, $ac3		\n"			\
	"	.word	0x00600810		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mflo0()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mflo	%0, $ac0		\n"			\
	"	.word	0x00000812		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mflo1()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mflo	%0, $ac1		\n"			\
	"	.word	0x00200812		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mflo2()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mflo	%0, $ac2		\n"			\
	"	.word	0x00400812		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mflo3()								\
({									\
	unsigned long __treg;						\
									\
	__asm__ __volatile__(						\
	"	.set	push			\n"			\
	"	.set	noat			\n"			\
	"	# mflo	%0, $ac3		\n"			\
	"	.word	0x00600812		\n"			\
	"	move	%0, $1			\n"			\
	"	.set	pop			\n"			\
	: "=r" (__treg));						\
	__treg;								\
})

#define mthi0(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mthi	$1, $ac0				\n"	\
	"	.word	0x00200011				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#define mthi1(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mthi	$1, $ac1				\n"	\
	"	.word	0x00200811				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#define mthi2(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mthi	$1, $ac2				\n"	\
	"	.word	0x00201011				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#define mthi3(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mthi	$1, $ac3				\n"	\
	"	.word	0x00201811				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#define mtlo0(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mtlo	$1, $ac0				\n"	\
	"	.word	0x00200013				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#define mtlo1(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mtlo	$1, $ac1				\n"	\
	"	.word	0x00200813				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#define mtlo2(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mtlo	$1, $ac2				\n"	\
	"	.word	0x00201013				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#define mtlo3(x)							\
do {									\
	__asm__ __volatile__(						\
	"	.set	push					\n"	\
	"	.set	noat					\n"	\
	"	move	$1, %0					\n"	\
	"	# mtlo	$1, $ac3				\n"	\
	"	.word	0x00201813				\n"	\
	"	.set	pop					\n"	\
	:								\
	: "r" (x));							\
} while (0)

#endif

/*
 * TLB operations.
 *
 * It is responsibility of the caller to take care of any TLB hazards.
 */
static inline void tlb_probe(void)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbp\n\t"
		".set reorder");
}

static inline void tlb_read(void)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbr\n\t"
		".set reorder");
}

static inline void tlb_write_indexed(void)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbwi\n\t"
		".set reorder");
}

static inline void tlb_write_random(void)
{
	__asm__ __volatile__(
		".set noreorder\n\t"
		"tlbwr\n\t"
		".set reorder");
}

/*
 * Manipulate bits in a c0 register.
 */
#define __BUILD_SET_C0(name)					\
static inline unsigned int					\
set_c0_##name(unsigned int set)					\
{								\
	unsigned int res;					\
								\
	res = read_c0_##name();					\
	res |= set;						\
	write_c0_##name(res);					\
								\
	return res;						\
}								\
								\
static inline unsigned int					\
clear_c0_##name(unsigned int clear)				\
{								\
	unsigned int res;					\
								\
	res = read_c0_##name();					\
	res &= ~clear;						\
	write_c0_##name(res);					\
								\
	return res;						\
}								\
								\
static inline unsigned int					\
change_c0_##name(unsigned int change, unsigned int new)		\
{								\
	unsigned int res;					\
								\
	res = read_c0_##name();					\
	res &= ~change;						\
	res |= (new & change);					\
	write_c0_##name(res);					\
								\
	return res;						\
}

__BUILD_SET_C0(status)
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
__BUILD_SET_C0(intcontrol)

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_MIPSREGS_H */