csb655.h~

umon bootloader source code, support mips cpu.

/* Cogent CSB655 SBC
 *
 *   Copyright (C) 2004 Cadenux, LLC (http://www.cadenux.com)
 *   Gregory Nutt ([e-mail])
 *
 * Based on linux/include/asm-mips/arch-db1x00/db1x00.h
 *
 *   Copyright 2001 MontaVista Software Inc.
 *   Author: MontaVista Software, Inc.
 *           [e-mail] or [e-mail]
 *
 * This program is free software; you can distribute it and/or modify it
 * under the terms of the GNU General Public License (Version 2) as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 */

#ifndef __ASM_ARCH_CSB655_H
#define __ASM_ARCH_CSB655_H

/* The operating frequence of the CSB655 is given here */

#define AU1100_CPU_CLOCK 396000000

/* The Au1550 has 32 Primary GPIO pins labelled 0-31 and it has 16 Secodary
 * GPIO pins labelled 200-215
 *
 * When GPIO2 block GPIOs are used as outputs the PGIO enable output must be 
 * used (upper 16 bits of register)
 */
 
/* COGENT CSB655 AU1100 Compact Flash Interface
 * 
 * Standard Au1100 GPIO usage (See discussion of above for additional
 * information):
 *
 * GPIO     Signal    In/Out Active Comments
 * ----------------------------------------------------------------------
 * GPIO-001  GPIO_001   In           CF IRQ/RDY (input)
 * GPIO-006  GPIO_006   In           CF CD
 * GPIO-203  GPIO_203   Out    High  CF_RST (output, 1 = reset)
 * GPIO-205  GPIO_205   Out    High  CF_PWR (output, 1 = on)
 */

#define CSB655_GPIO_CFRDY	(1<<1)
#define CSB655_GPIO_CF_CD	(1<<6)
#define CSB655_GPIO_CF_RST	(1 << 3) 
#define CSB655_GPIO_CF_RSTEN	(1 << 19)	/* use output enable for block2 */
#define CSB655_GPIO_CF_PWR	(1 << 5) 
#define CSB655_GPIO_CF_PWREN	(1 << 21)	/* use output enable for block2 */

#define PCMCIA_MAX_SOCK 1
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)

/* PCI and USB require a 5V VCC to be enabled via GPIO-7 */
#define CSB655_GPIO_VCC5EN	(1 << 7)

#endif /* __ASM_ARCH_CSB655_H */