au1000_old.h

umon bootloader source code, support mips cpu.

/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for Alchemy Semiconductor's Au1k CPU.
 *
 * Copyright 2000,2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	[e-mail] or [e-mail]
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

 /*
  * some definitions add by [e-mail] and [e-mail]
  */

#ifndef _AU1000_H_
#define _AU1000_H_

#include <linux/config.h>

#ifndef _LANGUAGE_ASSEMBLY

#include <linux/delay.h>
#include <asm/io.h>

/* cpu pipeline flush */
void static inline au_sync(void)
{
	__asm__ volatile ("sync");
}

void static inline au_sync_udelay(int us)
{
	__asm__ volatile ("sync");
	udelay(us);
}

void static inline au_sync_delay(int ms)
{
	__asm__ volatile ("sync");
	mdelay(ms);
}

void static inline au_writeb(u8 val, unsigned long reg)
{
	*(volatile u8 *)(reg) = val;
}

void static inline au_writew(u16 val, unsigned long reg)
{
	*(volatile u16 *)(reg) = val;
}

void static inline au_writel(u32 val, unsigned long reg)
{
	*(volatile u32 *)(reg) = val;
}

static inline u8 au_readb(unsigned long reg)
{
	return (*(volatile u8 *)reg);
}

static inline u16 au_readw(unsigned long reg)
{
	return (*(volatile u16 *)reg);
}

static inline u32 au_readl(unsigned long reg)
{
	return (*(volatile u32 *)reg);
}

/* These next three functions should be a generic part of the MIPS
 * kernel (with the 'au_' removed from the name) and selected for
 * processors that support the instructions.
 * Taken from PPC tree.  -- Dan
 */
/* Return the bit position of the most significant 1 bit in a word */
static __inline__ int __ilog2(unsigned int x)
{
	int lz;

	asm volatile (
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips32\n\t"
		"clz\t%0,%1\n\t"
		".set\tmips0\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (lz)
		: "r" (x));

	return 31 - lz;
}

static __inline__ int au_ffz(unsigned int x)
{
	if ((x = ~x) == 0)
		return 32;
	return __ilog2(x & -x);
}

/*
 * ffs: find first bit set. This is defined the same way as
 * the libc and compiler builtin ffs routines, therefore
 * differs in spirit from the above ffz (man ffs).
 */
static __inline__ int au_ffs(int x)
{
	return __ilog2(x & -x) + 1;
}

/* arch/mips/au1000/common/clocks.c */
extern void set_au1x00_speed(unsigned int new_freq);
extern unsigned int get_au1x00_speed(void);
extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
extern unsigned long get_au1x00_uart_baud_base(void);
extern void set_au1x00_lcd_clock(void);
extern unsigned int get_au1x00_lcd_clock(void);

/*
 * Every board describes its IRQ mapping with this table.
 */
typedef struct au1xxx_irqmap {
	int	im_irq;
	int	im_type;
	int	im_request;
} au1xxx_irq_map_t;

/*
 * init_IRQ looks for a table with this name.
 */
extern au1xxx_irq_map_t au1xxx_irq_map[];

#endif /* !defined (_LANGUAGE_ASSEMBLY) */

#ifdef CONFIG_PM
/* no CP0 timer irq */
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
#else
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
#endif

/*
 * SDRAM Register Offsets
 */
#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
#define MEM_SDMODE0		(0x0000)
#define MEM_SDMODE1		(0x0004)
#define MEM_SDMODE2		(0x0008)
#define MEM_SDADDR0		(0x000C)
#define MEM_SDADDR1		(0x0010)
#define MEM_SDADDR2		(0x0014)
#define MEM_SDREFCFG	(0x0018)
#define MEM_SDPRECMD	(0x001C)
#define MEM_SDAUTOREF	(0x0020)
#define MEM_SDWRMD0		(0x0024)
#define MEM_SDWRMD1		(0x0028)
#define MEM_SDWRMD2		(0x002C)
#define MEM_SDSLEEP		(0x0030)
#define MEM_SDSMCKE		(0x0034)

/*
 * MEM_SDMODE register content definitions
 */
#define MEM_SDMODE_F		(1<<22)
#define MEM_SDMODE_SR		(1<<21)
#define MEM_SDMODE_BS		(1<<20)
#define MEM_SDMODE_RS		(3<<18)
#define MEM_SDMODE_CS		(7<<15)
#define MEM_SDMODE_TRAS		(15<<11)
#define MEM_SDMODE_TMRD		(3<<9)
#define MEM_SDMODE_TWR		(3<<7)
#define MEM_SDMODE_TRP		(3<<5)
#define MEM_SDMODE_TRCD		(3<<3)
#define MEM_SDMODE_TCL		(7<<0)

#define MEM_SDMODE_BS_2Bank	(0<<20)
#define MEM_SDMODE_BS_4Bank	(1<<20)
#define MEM_SDMODE_RS_11Row	(0<<18)
#define MEM_SDMODE_RS_12Row	(1<<18)
#define MEM_SDMODE_RS_13Row	(2<<18)
#define MEM_SDMODE_RS_N(N)	((N)<<18)
#define MEM_SDMODE_CS_7Col	(0<<15)
#define MEM_SDMODE_CS_8Col	(1<<15)
#define MEM_SDMODE_CS_9Col	(2<<15)
#define MEM_SDMODE_CS_10Col	(3<<15)
#define MEM_SDMODE_CS_11Col	(4<<15)
#define MEM_SDMODE_CS_N(N)		((N)<<15)
#define MEM_SDMODE_TRAS_N(N)	((N)<<11)
#define MEM_SDMODE_TMRD_N(N)	((N)<<9)
#define MEM_SDMODE_TWR_N(N)		((N)<<7)
#define MEM_SDMODE_TRP_N(N)		((N)<<5)
#define MEM_SDMODE_TRCD_N(N)	((N)<<3)
#define MEM_SDMODE_TCL_N(N)		((N)<<0)

/*
 * MEM_SDADDR register contents definitions
 */
#define MEM_SDADDR_E			(1<<20)
#define MEM_SDADDR_CSBA			(0x03FF<<10)
#define MEM_SDADDR_CSMASK		(0x03FF<<0)
#define MEM_SDADDR_CSBA_N(N)	((N)&(0x03FF<<22)>>12)
#define MEM_SDADDR_CSMASK_N(N)	((N)&(0x03FF<<22)>>22)

/*
 * MEM_SDREFCFG register content definitions
 */
#define MEM_SDREFCFG_TRC		(15<<28)
#define MEM_SDREFCFG_TRPM		(3<<26)
#define MEM_SDREFCFG_E			(1<<25)
#define MEM_SDREFCFG_RE			(0x1ffffff<<0)
#define MEM_SDREFCFG_TRC_N(N)	((N)<<MEM_SDREFCFG_TRC)
#define MEM_SDREFCFG_TRPM_N(N)	((N)<<MEM_SDREFCFG_TRPM)
#define MEM_SDREFCFG_REF_N(N)	(N)
#endif

/***********************************************************************/

/*
 * Au1550 SDRAM Register Offsets
 */

/***********************************************************************/

//zx,modify #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
#if defined(CONFIG_SOC_AU1200)
#define MEM_SDMODE0		(0x0800)
#define MEM_SDMODE1		(0x0808)
#define MEM_SDMODE2		(0x0810)
#define MEM_SDADDR0		(0x0820)
#define MEM_SDADDR1		(0x0828)
#define MEM_SDADDR2		(0x0830)
#define MEM_SDCONFIGA	(0x0840)
#define MEM_SDCONFIGB	(0x0848)
#define MEM_SDSTAT		(0x0850)
#define MEM_SDERRADDR	(0x0858)
#define MEM_SDSTRIDE0	(0x0860)
#define MEM_SDSTRIDE1	(0x0868)
#define MEM_SDSTRIDE2	(0x0870)
#define MEM_SDWRMD0		(0x0880)
#define MEM_SDWRMD1		(0x0888)
#define MEM_SDWRMD2		(0x0890)
#define MEM_SDPRECMD	(0x08C0)
#define MEM_SDAUTOREF	(0x08C8)
#define MEM_SDSREF		(0x08D0)
#define MEM_SDSLEEP		MEM_SDSREF

#endif

/*
 * Physical base addresses for integrated peripherals
 */

#ifdef CONFIG_SOC_AU1000
#define	MEM_PHYS_ADDR		0x14000000
#define	STATIC_MEM_PHYS_ADDR	0x14001000
#define	DMA0_PHYS_ADDR		0x14002000
#define	DMA1_PHYS_ADDR		0x14002100
#define	DMA2_PHYS_ADDR		0x14002200
#define	DMA3_PHYS_ADDR		0x14002300
#define	DMA4_PHYS_ADDR		0x14002400
#define	DMA5_PHYS_ADDR		0x14002500
#define	DMA6_PHYS_ADDR		0x14002600
#define	DMA7_PHYS_ADDR		0x14002700
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define	AC97_PHYS_ADDR		0x10000000
#define	USBH_PHYS_ADDR		0x10100000
#define	USBD_PHYS_ADDR		0x10200000
#define	IRDA_PHYS_ADDR		0x10300000
#define	MAC0_PHYS_ADDR		0x10500000
#define	MAC1_PHYS_ADDR		0x10510000
#define	MACEN_PHYS_ADDR		0x10520000
#define	MACDMA0_PHYS_ADDR	0x14004000
#define	MACDMA1_PHYS_ADDR	0x14004200
#define	I2S_PHYS_ADDR		0x11000000
#define	UART0_PHYS_ADDR		0x11100000
#define	UART1_PHYS_ADDR		0x11200000
#define	UART2_PHYS_ADDR		0x11300000
#define	UART3_PHYS_ADDR		0x11400000
#define	SSI0_PHYS_ADDR		0x11600000
#define	SSI1_PHYS_ADDR		0x11680000
#define	SYS_PHYS_ADDR		0x11900000
#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
#endif

/********************************************************************/

#ifdef CONFIG_SOC_AU1500
#define	MEM_PHYS_ADDR		0x14000000
#define	STATIC_MEM_PHYS_ADDR	0x14001000
#define	DMA0_PHYS_ADDR		0x14002000
#define	DMA1_PHYS_ADDR		0x14002100
#define	DMA2_PHYS_ADDR		0x14002200
#define	DMA3_PHYS_ADDR		0x14002300
#define	DMA4_PHYS_ADDR		0x14002400
#define	DMA5_PHYS_ADDR		0x14002500
#define	DMA6_PHYS_ADDR		0x14002600
#define	DMA7_PHYS_ADDR		0x14002700
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define	AC97_PHYS_ADDR		0x10000000
#define	USBH_PHYS_ADDR		0x10100000
#define	USBD_PHYS_ADDR		0x10200000
#define PCI_PHYS_ADDR		0x14005000
#define	MAC0_PHYS_ADDR		0x11500000
#define	MAC1_PHYS_ADDR		0x11510000
#define	MACEN_PHYS_ADDR		0x11520000
#define	MACDMA0_PHYS_ADDR	0x14004000
#define	MACDMA1_PHYS_ADDR	0x14004200
#define	I2S_PHYS_ADDR		0x11000000
#define	UART0_PHYS_ADDR		0x11100000
#define	UART3_PHYS_ADDR		0x11400000
#define GPIO2_PHYS_ADDR		0x11700000
#define	SYS_PHYS_ADDR		0x11900000
#define PCI_MEM_PHYS_ADDR     0x400000000ULL
#define PCI_IO_PHYS_ADDR      0x500000000ULL
#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
#endif

/********************************************************************/

#ifdef CONFIG_SOC_AU1100
#define	MEM_PHYS_ADDR		0x14000000
#define	STATIC_MEM_PHYS_ADDR	0x14001000
#define	DMA0_PHYS_ADDR		0x14002000
#define	DMA1_PHYS_ADDR		0x14002100
#define	DMA2_PHYS_ADDR		0x14002200
#define	DMA3_PHYS_ADDR		0x14002300
#define	DMA4_PHYS_ADDR		0x14002400