au1000.h

umon bootloader source code, support mips cpu.

/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for Alchemy Semiconductor's Au1k CPU.
 *
 * Copyright 2000,2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	[e-mail] or [e-mail]
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

 /*
  * some definitions add by [e-mail] and [e-mail]
  */

#ifndef _AU1000_H_
#define _AU1000_H_

#include <linux/config.h>

#ifndef _LANGUAGE_ASSEMBLY

#include <linux/delay.h>
#include <asm/io.h>

/* cpu pipeline flush */
void static inline au_sync(void)
{
	__asm__ volatile ("sync");
}

void static inline au_sync_udelay(int us)
{
	__asm__ volatile ("sync");
	udelay(us);
}

void static inline au_sync_delay(int ms)
{
	__asm__ volatile ("sync");
	mdelay(ms);
}

void static inline au_writeb(u8 val, unsigned long reg)
{
	*(volatile u8 *)(reg) = val;
}

void static inline au_writew(u16 val, unsigned long reg)
{
	*(volatile u16 *)(reg) = val;
}

void static inline au_writel(u32 val, unsigned long reg)
{
	*(volatile u32 *)(reg) = val;
}

static inline u8 au_readb(unsigned long reg)
{
	return (*(volatile u8 *)reg);
}

static inline u16 au_readw(unsigned long reg)
{
	return (*(volatile u16 *)reg);
}

static inline u32 au_readl(unsigned long reg)
{
	return (*(volatile u32 *)reg);
}

/* These next three functions should be a generic part of the MIPS
 * kernel (with the 'au_' removed from the name) and selected for
 * processors that support the instructions.
 * Taken from PPC tree.  -- Dan
 */
/* Return the bit position of the most significant 1 bit in a word */
static __inline__ int __ilog2(unsigned int x)
{
	int lz;

	asm volatile (
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips32\n\t"
		"clz\t%0,%1\n\t"
		".set\tmips0\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (lz)
		: "r" (x));

	return 31 - lz;
}

static __inline__ int au_ffz(unsigned int x)
{
	if ((x = ~x) == 0)
		return 32;
	return __ilog2(x & -x);
}

/*
 * ffs: find first bit set. This is defined the same way as
 * the libc and compiler builtin ffs routines, therefore
 * differs in spirit from the above ffz (man ffs).
 */
static __inline__ int au_ffs(int x)
{
	return __ilog2(x & -x) + 1;
}

/* arch/mips/au1000/common/clocks.c */
extern void set_au1x00_speed(unsigned int new_freq);
extern unsigned int get_au1x00_speed(void);
extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
extern unsigned long get_au1x00_uart_baud_base(void);
extern void set_au1x00_lcd_clock(void);
extern unsigned int get_au1x00_lcd_clock(void);

/*
 * Every board describes its IRQ mapping with this table.
 */
typedef struct au1xxx_irqmap {
	int	im_irq;
	int	im_type;
	int	im_request;
} au1xxx_irq_map_t;

/*
 * init_IRQ looks for a table with this name.
 */
extern au1xxx_irq_map_t au1xxx_irq_map[];

#endif /* !defined (_LANGUAGE_ASSEMBLY) */

#ifdef CONFIG_PM
/* no CP0 timer irq */
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
#else
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
#endif

/***********************************************************************/

/*
 * Au1550 SDRAM Register Offsets
 */

/***********************************************************************/


/*
 * Physical base addresses for integrated peripherals
 */

/***********************************************************************/
#ifdef CONFIG_SOC_AU1550
#define RISC_PHYS_ADDR	0x8000000
#define CCTL_PHYS_ADDR	0x8010000
#define MC_PHYS_ADDR		0x8020000
#define SIF_PHYS_ADDR		0x8030000
#define SC_PHYS_ADDR		0x8040000
#define VIN_PHYS_ADDR		0x8050000
#define VOUT_PHYS_ADDR	0x8060000
#define AUD_PHYS_ADDR		0x8070000
#define DMAC_PHYS_ADDR	0x8080000
#define PPE_PHYS_ADDR		0x8090000
#define PIF_PHYS_ADDR		0x80A0000
#define VSC_PHYS_ADDR		0x80B0000
#define EMAC0_PHYS_ADDR	0x80C0000
#define EMAC1_PHYS_ADDR 	0x80D0000
#define SEC_PHYS_ADDR		0x80E0000
#define UART_PHYS_ADDR	0x80F0000

#endif

/***********************************************************************/


/* Interrupt Numbers */
#ifdef CONFIG_SOC_AU1550
#define NAND_INTR 	0
#define CCTL_INTR 	1
#define MC_INTR		2
#define SIF_INTR	3
#define SC_INTR		4
#define VIN_INTR	5
#define VOUT_INTR	6
#define AUD_INTR	7
#define DMAC_INTR	8
#define PPE_INTR	9
#define PIF_INTR	10
#define VSC_INTR	11
#define ETH0_INTR	12
#define ETH1_INTR	13
#define SEC_INTR	14
#define UART_INTR	15
#define SD_INTR		16
#define IDE_INTR	17
#define VCODEC_INTR	18
#define VCNT_INTR	19

#define ETH0_BASE      0xA80C0000
#define ETH1_BASE      0xA80D0000
#define MAC0_ENABLE       EMAC0_REGS_ADDR(ETH_CTL)
#define MAC1_ENABLE       EMAC1_REGS_ADDR(ETH_CTL)
#define NUM_ETH_INTERFACES 2





#endif /* CONFIG_SOC_AU1550 */