gt96100.h

umon bootloader source code, support mips cpu.

#define GT96100_MPSC_CHAN1_REG8         0x008A28
#define GT96100_MPSC_CHAN1_REG9         0x008A2C
#define GT96100_MPSC_CHAN1_REG10        0x008A30
#define GT96100_MPSC_CHAN1_REG11        0x008A34
#define GT96100_MPSC2_MAIN_CONFIG_LOW   0x010A00
#define GT96100_MPSC2_MAIN_CONFIG_HIGH  0x010A04
#define GT96100_MPSC2_PROTOCOL_CONFIG   0x010A08
#define GT96100_MPSC_CHAN2_REG1         0x010A0C
#define GT96100_MPSC_CHAN2_REG2         0x010A10
#define GT96100_MPSC_CHAN2_REG3         0x010A14
#define GT96100_MPSC_CHAN2_REG4         0x010A18
#define GT96100_MPSC_CHAN2_REG5         0x010A1C
#define GT96100_MPSC_CHAN2_REG6         0x010A20
#define GT96100_MPSC_CHAN2_REG7         0x010A24
#define GT96100_MPSC_CHAN2_REG8         0x010A28
#define GT96100_MPSC_CHAN2_REG9         0x010A2C
#define GT96100_MPSC_CHAN2_REG10        0x010A30
#define GT96100_MPSC_CHAN2_REG11        0x010A34
#define GT96100_MPSC3_MAIN_CONFIG_LOW   0x018A00
#define GT96100_MPSC3_MAIN_CONFIG_HIGH  0x018A04
#define GT96100_MPSC3_PROTOCOL_CONFIG   0x018A08
#define GT96100_MPSC_CHAN3_REG1         0x018A0C
#define GT96100_MPSC_CHAN3_REG2         0x018A10
#define GT96100_MPSC_CHAN3_REG3         0x018A14
#define GT96100_MPSC_CHAN3_REG4         0x018A18
#define GT96100_MPSC_CHAN3_REG5         0x018A1C
#define GT96100_MPSC_CHAN3_REG6         0x018A20
#define GT96100_MPSC_CHAN3_REG7         0x018A24
#define GT96100_MPSC_CHAN3_REG8         0x018A28
#define GT96100_MPSC_CHAN3_REG9         0x018A2C
#define GT96100_MPSC_CHAN3_REG10        0x018A30
#define GT96100_MPSC_CHAN3_REG11        0x018A34
#define GT96100_MPSC4_MAIN_CONFIG_LOW   0x020A00
#define GT96100_MPSC4_MAIN_CONFIG_HIGH  0x020A04
#define GT96100_MPSC4_PROTOCOL_CONFIG   0x020A08
#define GT96100_MPSC_CHAN4_REG1         0x020A0C
#define GT96100_MPSC_CHAN4_REG2         0x020A10
#define GT96100_MPSC_CHAN4_REG3         0x020A14
#define GT96100_MPSC_CHAN4_REG4         0x020A18
#define GT96100_MPSC_CHAN4_REG5         0x020A1C
#define GT96100_MPSC_CHAN4_REG6         0x020A20
#define GT96100_MPSC_CHAN4_REG7         0x020A24
#define GT96100_MPSC_CHAN4_REG8         0x020A28
#define GT96100_MPSC_CHAN4_REG9         0x020A2C
#define GT96100_MPSC_CHAN4_REG10        0x020A30
#define GT96100_MPSC_CHAN4_REG11        0x020A34
#define GT96100_MPSC5_MAIN_CONFIG_LOW   0x028A00
#define GT96100_MPSC5_MAIN_CONFIG_HIGH  0x028A04
#define GT96100_MPSC5_PROTOCOL_CONFIG   0x028A08
#define GT96100_MPSC_CHAN5_REG1         0x028A0C
#define GT96100_MPSC_CHAN5_REG2         0x028A10
#define GT96100_MPSC_CHAN5_REG3         0x028A14
#define GT96100_MPSC_CHAN5_REG4         0x028A18
#define GT96100_MPSC_CHAN5_REG5         0x028A1C
#define GT96100_MPSC_CHAN5_REG6         0x028A20
#define GT96100_MPSC_CHAN5_REG7         0x028A24
#define GT96100_MPSC_CHAN5_REG8         0x028A28
#define GT96100_MPSC_CHAN5_REG9         0x028A2C
#define GT96100_MPSC_CHAN5_REG10        0x028A30
#define GT96100_MPSC_CHAN5_REG11        0x028A34
#define GT96100_MPSC6_MAIN_CONFIG_LOW   0x030A00
#define GT96100_MPSC6_MAIN_CONFIG_HIGH  0x030A04
#define GT96100_MPSC6_PROTOCOL_CONFIG   0x030A08
#define GT96100_MPSC_CHAN6_REG1         0x030A0C
#define GT96100_MPSC_CHAN6_REG2         0x030A10
#define GT96100_MPSC_CHAN6_REG3         0x030A14
#define GT96100_MPSC_CHAN6_REG4         0x030A18
#define GT96100_MPSC_CHAN6_REG5         0x030A1C
#define GT96100_MPSC_CHAN6_REG6         0x030A20
#define GT96100_MPSC_CHAN6_REG7         0x030A24
#define GT96100_MPSC_CHAN6_REG8         0x030A28
#define GT96100_MPSC_CHAN6_REG9         0x030A2C
#define GT96100_MPSC_CHAN6_REG10        0x030A30
#define GT96100_MPSC_CHAN6_REG11        0x030A34
#define GT96100_MPSC7_MAIN_CONFIG_LOW   0x038A00
#define GT96100_MPSC7_MAIN_CONFIG_HIGH  0x038A04
#define GT96100_MPSC7_PROTOCOL_CONFIG   0x038A08
#define GT96100_MPSC_CHAN7_REG1         0x038A0C
#define GT96100_MPSC_CHAN7_REG2         0x038A10
#define GT96100_MPSC_CHAN7_REG3         0x038A14
#define GT96100_MPSC_CHAN7_REG4         0x038A18
#define GT96100_MPSC_CHAN7_REG5         0x038A1C
#define GT96100_MPSC_CHAN7_REG6         0x038A20
#define GT96100_MPSC_CHAN7_REG7         0x038A24
#define GT96100_MPSC_CHAN7_REG8         0x038A28
#define GT96100_MPSC_CHAN7_REG9         0x038A2C
#define GT96100_MPSC_CHAN7_REG10        0x038A30
#define GT96100_MPSC_CHAN7_REG11        0x038A34
/*  FlexTDMs  */
/* TDPR0 - Transmit Dual Port RAM. block size 0xff */
#define GT96100_FXTDM0_TDPR0_BLK0_BASE  0x000B00
#define GT96100_FXTDM0_TDPR0_BLK1_BASE  0x001B00
#define GT96100_FXTDM0_TDPR0_BLK2_BASE  0x002B00
#define GT96100_FXTDM0_TDPR0_BLK3_BASE  0x003B00
/* RDPR0 - Receive Dual Port RAM. block size 0xff */
#define GT96100_FXTDM0_RDPR0_BLK0_BASE  0x004B00
#define GT96100_FXTDM0_RDPR0_BLK1_BASE  0x005B00
#define GT96100_FXTDM0_RDPR0_BLK2_BASE  0x006B00
#define GT96100_FXTDM0_RDPR0_BLK3_BASE  0x007B00
#define GT96100_FXTDM0_TX_READ_PTR      0x008B00
#define GT96100_FXTDM0_RX_READ_PTR      0x008B04
#define GT96100_FXTDM0_CONFIG       0x008B08
#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C
#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10
#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14
#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18
#define GT96100_FXTDM1_TDPR1_BLK0_BASE  0x010B00
#define GT96100_FXTDM1_TDPR1_BLK1_BASE  0x011B00
#define GT96100_FXTDM1_TDPR1_BLK2_BASE  0x012B00
#define GT96100_FXTDM1_TDPR1_BLK3_BASE  0x013B00
#define GT96100_FXTDM1_RDPR1_BLK0_BASE  0x014B00
#define GT96100_FXTDM1_RDPR1_BLK1_BASE  0x015B00
#define GT96100_FXTDM1_RDPR1_BLK2_BASE  0x016B00
#define GT96100_FXTDM1_RDPR1_BLK3_BASE  0x017B00
#define GT96100_FXTDM1_TX_READ_PTR      0x018B00
#define GT96100_FXTDM1_RX_READ_PTR      0x018B04
#define GT96100_FXTDM1_CONFIG       0x018B08
#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C
#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10
#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14
#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18
#define GT96100_FLTDM2_TDPR2_BLK0_BASE  0x020B00
#define GT96100_FLTDM2_TDPR2_BLK1_BASE  0x021B00
#define GT96100_FLTDM2_TDPR2_BLK2_BASE  0x022B00
#define GT96100_FLTDM2_TDPR2_BLK3_BASE  0x023B00
#define GT96100_FLTDM2_RDPR2_BLK0_BASE  0x024B00
#define GT96100_FLTDM2_RDPR2_BLK1_BASE  0x025B00
#define GT96100_FLTDM2_RDPR2_BLK2_BASE  0x026B00
#define GT96100_FLTDM2_RDPR2_BLK3_BASE  0x027B00
#define GT96100_FLTDM2_TX_READ_PTR      0x028B00
#define GT96100_FLTDM2_RX_READ_PTR      0x028B04
#define GT96100_FLTDM2_CONFIG       0x028B08
#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C
#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10
#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14
#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18
#define GT96100_FLTDM3_TDPR3_BLK0_BASE  0x030B00
#define GT96100_FLTDM3_TDPR3_BLK1_BASE  0x031B00
#define GT96100_FLTDM3_TDPR3_BLK2_BASE  0x032B00
#define GT96100_FLTDM3_TDPR3_BLK3_BASE  0x033B00
#define GT96100_FXTDM3_RDPR3_BLK0_BASE  0x034B00
#define GT96100_FXTDM3_RDPR3_BLK1_BASE  0x035B00
#define GT96100_FXTDM3_RDPR3_BLK2_BASE  0x036B00
#define GT96100_FXTDM3_RDPR3_BLK3_BASE  0x037B00
#define GT96100_FXTDM3_TX_READ_PTR      0x038B00
#define GT96100_FXTDM3_RX_READ_PTR      0x038B04
#define GT96100_FXTDM3_CONFIG       0x038B08
#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C
#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10
#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14
#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18
/*  Baud Rate Generators  */
#define GT96100_BRG0_CONFIG     0x102A00
#define GT96100_BRG0_BAUD_TUNE  0x102A04
#define GT96100_BRG1_CONFIG     0x102A08
#define GT96100_BRG1_BAUD_TUNE  0x102A0C
#define GT96100_BRG2_CONFIG     0x102A10
#define GT96100_BRG2_BAUD_TUNE  0x102A14
#define GT96100_BRG3_CONFIG     0x102A18
#define GT96100_BRG3_BAUD_TUNE  0x102A1C
#define GT96100_BRG4_CONFIG     0x102A20
#define GT96100_BRG4_BAUD_TUNE  0x102A24
#define GT96100_BRG5_CONFIG     0x102A28
#define GT96100_BRG5_BAUD_TUNE  0x102A2C
#define GT96100_BRG6_CONFIG     0x102A30
#define GT96100_BRG6_BAUD_TUNE  0x102A34
#define GT96100_BRG7_CONFIG     0x102A38
#define GT96100_BRG7_BAUD_TUNE  0x102A3C
/*  Routing Registers  */
#define GT96100_ROUTE_MAIN      0x101A00
#define GT96100_ROUTE_RX_CLOCK  0x101A10
#define GT96100_ROUTE_TX_CLOCK  0x101A20
/*  General Purpose Ports  */
#define GT96100_GPP_CONFIG0     0x100A00
#define GT96100_GPP_CONFIG1     0x100A04
#define GT96100_GPP_CONFIG2     0x100A08
#define GT96100_GPP_CONFIG3     0x100A0C
#define GT96100_GPP_IO0         0x100A20
#define GT96100_GPP_IO1         0x100A24
#define GT96100_GPP_IO2         0x100A28
#define GT96100_GPP_IO3         0x100A2C
#define GT96100_GPP_DATA0       0x100A40
#define GT96100_GPP_DATA1       0x100A44
#define GT96100_GPP_DATA2       0x100A48
#define GT96100_GPP_DATA3       0x100A4C
#define GT96100_GPP_LEVEL0      0x100A60
#define GT96100_GPP_LEVEL1      0x100A64
#define GT96100_GPP_LEVEL2      0x100A68
#define GT96100_GPP_LEVEL3      0x100A6C
/*  Watchdog  */
#define GT96100_WD_CONFIG   0x101A80
#define GT96100_WD_VALUE    0x101A84
/* Communication Unit Arbiter  */
#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0
/*  PCI Arbiters  */
#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0
#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4
/* CIU Arbiter */
#define GT96100_CIU_ARBITER_CONFIG 0x101AC0
/* Interrupt Controller */
#define GT96100_MAIN_CAUSE     0x000C18
#define GT96100_INT0_MAIN_MASK 0x000C1C
#define GT96100_INT1_MAIN_MASK 0x000C24
#define GT96100_HIGH_CAUSE     0x000C98
#define GT96100_INT0_HIGH_MASK 0x000C9C
#define GT96100_INT1_HIGH_MASK 0x000CA4
#define GT96100_INT0_SELECT    0x000C70
#define GT96100_INT1_SELECT    0x000C74
#define GT96100_SERIAL_CAUSE   0x103A00
#define GT96100_SERINT0_MASK   0x103A80
#define GT96100_SERINT1_MASK   0x103A88

#endif /*  _GT96100_H */